mb/starlabs/*: Increase size of SMMSTORE region to 512KB
The previous default size of 256KB provided for only 64KB of actual space for EFI variables, and after accounting for fragmentation, did not provide enough free space for applying updates, such as for the UEFI revocation database (DBX). Increasing it to 512KB allows for 192KB space for variables, and allows the UEFI DBX to be updated properly via fwupd. TEST=build/boot starlite_adl, verify UEFI DBX able to be successfully updated via fwupd. Change-Id: I0fd28e38f5d3ad1e4db33fa3ab075929044ac831 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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12 changed files with 35 additions and 35 deletions
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@ -6,9 +6,9 @@ FLASH 0x1000000 {
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SI_BIOS 0xa00000 {
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EC@0x0 0x20000
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RW_MRC_CACHE@0x20000 0x10000
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SMMSTORE@0x30000 0x40000
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CONSOLE@0x70000 0x20000
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FMAP@0x90000 0x1000
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SMMSTORE@0x30000 0x80000
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CONSOLE@0xB0000 0x20000
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FMAP@0xD0000 0x1000
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COREBOOT(CBFS)
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}
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}
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@ -44,7 +44,7 @@
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# the header.
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FLASH 8M {
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OBBP@0x382000 {
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OBB@0x0 0x2ae000 {
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OBB@0x0 0x2ee000 {
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FMAP@0xe000 0x10000
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COREBOOT(CBFS)@0x1e000 0x210000
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FPF_STATUS@0x22e000 0x10000
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@ -53,7 +53,7 @@ FLASH 8M {
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RW_MRC_CACHE@0x10000 0x10000
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RW_VAR_MRC_CACHE@0x20000 0x10000
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}
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SMMSTORE@0x26e000 0x40000
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SMMSTORE@0x26e000 0x80000
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}
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}
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}
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@ -6,9 +6,9 @@ FLASH 0x2000000 {
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SI_BIOS 0x1000000 {
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EC@0x0 0x20000
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RW_MRC_CACHE@0x20000 0x10000
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SMMSTORE@0x30000 0x40000
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CONSOLE@0x70000 0x20000
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FMAP@0x90000 0x1000
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SMMSTORE@0x30000 0x80000
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CONSOLE@0xB0000 0x20000
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FMAP@0xD0000 0x1000
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COREBOOT(CBFS)
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}
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}
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@ -6,9 +6,9 @@ FLASH 0x1000000 {
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SI_BIOS 0xa00000 {
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EC@0x0 0x20000
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RW_MRC_CACHE@0x20000 0x10000
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SMMSTORE@0x30000 0x40000
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CONSOLE@0x70000 0x20000
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FMAP@0x90000 0x1000
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SMMSTORE@0x30000 0x80000
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CONSOLE@0xB0000 0x20000
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FMAP@0xD0000 0x1000
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COREBOOT(CBFS)
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}
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}
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@ -6,9 +6,9 @@ FLASH 16M {
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BIOS@0x400000 0xC00000 {
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EC@0x0 0x20000
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RW_MRC_CACHE@0x20000 0x10000
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SMMSTORE@0x30000 0x40000
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CONSOLE@0x70000 0x20000
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FMAP@0x90000 0x200
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SMMSTORE@0x30000 0x80000
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CONSOLE@0xB0000 0x20000
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FMAP@0xD0000 0x200
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COREBOOT(CBFS)
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}
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}
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@ -1,9 +1,9 @@
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FLASH 8M {
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BIOS@0x200000 0x600000 {
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RW_MRC_CACHE@0x0 0x10000
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SMMSTORE@0x10000 0x40000
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CONSOLE@0x50000 0x20000
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FMAP@0x70000 0x200
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SMMSTORE@0x10000 0x80000
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CONSOLE@0x90000 0x20000
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FMAP@0xB0000 0x200
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COREBOOT(CBFS)
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}
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}
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@ -6,9 +6,9 @@ FLASH 0x2000000 {
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SI_BIOS 0xe00000 {
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EC@0x0 0x20000
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RW_MRC_CACHE@0x20000 0x10000
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SMMSTORE@0x30000 0x40000
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CONSOLE@0x70000 0x20000
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FMAP@0x90000 0x1000
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SMMSTORE@0x30000 0x80000
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CONSOLE@0xB0000 0x20000
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FMAP@0xD0000 0x1000
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COREBOOT(CBFS)
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}
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}
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@ -6,9 +6,9 @@ FLASH 0x2000000 {
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SI_BIOS 0x1000000 {
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EC@0x0 0x20000
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RW_MRC_CACHE@0x20000 0x10000
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SMMSTORE@0x30000 0x40000
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CONSOLE@0x70000 0x20000
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FMAP@0x90000 0x1000
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SMMSTORE@0x30000 0x80000
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CONSOLE@0xB0000 0x20000
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FMAP@0xD0000 0x1000
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COREBOOT(CBFS)
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}
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}
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@ -6,9 +6,9 @@ FLASH 0x1000000 {
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SI_BIOS 0xb00000 {
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EC@0x0 0x20000
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RW_MRC_CACHE@0x20000 0x10000
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SMMSTORE@0x30000 0x40000
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CONSOLE@0x70000 0x20000
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FMAP@0x90000 0x1000
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SMMSTORE@0x30000 0x80000
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CONSOLE@0xB0000 0x20000
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FMAP@0xD0000 0x1000
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COREBOOT(CBFS)
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}
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}
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@ -6,9 +6,9 @@ FLASH 0x2000000 {
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SI_BIOS 0x1000000 {
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EC@0x0 0x20000
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RW_MRC_CACHE@0x20000 0x10000
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SMMSTORE@0x30000 0x40000
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CONSOLE@0x70000 0x20000
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FMAP@0x90000 0x1000
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SMMSTORE@0x30000 0x80000
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CONSOLE@0xB0000 0x20000
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FMAP@0xD0000 0x1000
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COREBOOT(CBFS)
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}
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}
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@ -6,9 +6,9 @@ FLASH 0x2000000 {
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SI_BIOS 0x1000000 {
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EC@0x0 0x20000
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RW_MRC_CACHE@0x20000 0x10000
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SMMSTORE@0x30000 0x40000
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CONSOLE@0x70000 0x20000
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FMAP@0x90000 0x1000
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SMMSTORE@0x30000 0x80000
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CONSOLE@0xB0000 0x20000
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FMAP@0xD0000 0x1000
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COREBOOT(CBFS)
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}
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}
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@ -6,9 +6,9 @@ FLASH 0x1000000 {
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SI_BIOS 0xa00000 {
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EC@0x0 0x20000
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RW_MRC_CACHE@0x20000 0x10000
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SMMSTORE@0x30000 0x40000
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CONSOLE@0x70000 0x20000
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FMAP@0x90000 0x1000
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SMMSTORE@0x30000 0x80000
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CONSOLE@0xB0000 0x20000
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FMAP@0xD0000 0x1000
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COREBOOT(CBFS)
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}
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}
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