Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: Ib964e4c2779fe467086681f55136237a69a8f736
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I08d7c39ba9be92d6a267d20068f41980a5042755
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: Ifa0b567c05e48c4f0f5dc2fc385cf5f82eb083a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: I728b71826798eb94c13e54aeadd3ca69c2bf5e8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87626
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add enums for the IGD aperture size and DVMT/stolen memory size, as is
done for newer SoCs. Use these enums rather than their int values
when configuring the IGD.
Change-Id: I369f9c73a00b41b056c89975d4c7e643f1e900c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87625
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add enums for the IGD aperture size and DVMT/stolen memory size, as is
done for newer SoCs. Use these enums rather than their int values
when configuring the IGD.
Change-Id: I16dbfcd1862ea0c43c62eef59e35ca144a1b2715
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87624
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the IGD UPDs for configuring the DVMT allocated memory and
the aperture size to the option API, so they can be configured via
CMOS/CFR. Default values are set to existing values if option API
is not used.
Add enums to map the DVMT and aperture size UPD values to user-
friendly ones, as was previously done for other SoCs.
Change-Id: Id85e698263b0193d0a83cd4d6ee6c10c89a1d2fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87623
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the IGD UPD for configuring the DVMT allocated memory to the
option API, so it can be configured via CMOS/CFR. Default value is set
to the existing fixed value of 128MB if option API is not used.
Change-Id: I413e958e3c02632c3920b39dd370b89ecc99613f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the IGD UPDs for configuring the DVMT allocated memory and
the aperture size to the option API, so they can be configured via
CMOS/CFR. Default values are set to existing values if option API
is not used.
Add enums to map the DVMT and aperture size UPD values to user-
friendly ones, as was previously done for Alder Lake SoC.
Change-Id: I1c9596d12864bf60449c4e54797a8761e07e2ee4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the IGD UPDs for configuring the DVMT allocated memory and
the aperture size to the option API, so they can be configured via
CMOS/CFR. Default values are set to existing values if option API
is not used.
Add an enum to map the aperture size UPD values to user-friendly ones,
as was already done for the DVMT size.
Change-Id: I03f100dff2d8a7f6bb87b9860c0be848e8aec61e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87620
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: Iec0b3b10b8cb78014ca1429be73ad2a6646f7de1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
In order to give SMM access to more than 4GiB on x86_64, update the
page table generation in the SMM loader.
Honor CONFIG_CPU_PT_ROM_MAP_GB and map the same amount of the address
space as done in other stages. This is required for SMM trying to access
the SPI BAR in high MMIO on AMD platforms.
TEST=Could access ROM3 BAR at 0xfd00000000 in SMM on AMD/birman+
Change-Id: Iae3dac8d39d3f5e55cc08aa96c8924f6364c5140
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87573
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Set the EDK2 PCD to COREv4 so that ACPI tables that are created by EDK2
always use the coreboot OEM ID instead of the default one ("INTEL").
The name is taken from: include/acpi/acpi.h (OEM_ID)
tested:
build and see that BGRT table contains COREv4 instead of INTEL as OEM
ID.
Change-Id: I5e3a7d0f133e5b790f59ea522a71647f72ffc79c
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87647
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The darp10 has a second fan but no dGPU. The NFAN Method must exist, so
use the default hwmon names of "fan1" and "fan2" for labels.
Change-Id: I553deefea374b9dd916be6611850fca61afd490d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Fixes using USB3 devices at USB3 speeds in all ports.
This fix requires `EnableTcssCovTypeA`, which is not available in the
coreboot FSP headers and not available upstream as Intel will not make a
Client FSP release.
Change-Id: I9bc6c5fc4c13bfa2e31ee1ce334b91e151373b6e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
dt_find_node() looks up nodes specified by the `const char **path`
array, without modifying the strings in the array. Therefore, the char
pointers in the array could be changed to const.
Change-Id: I8d330e78d0977bae54996bb622190f6546fcb59f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Let coreboot configure the eSPI GPIOs, to ensure they are correct
rather than letting FSP do it.
Change-Id: I14dc740be9a770b662dd61bfdc4f4ace8973d998
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: Icec6dd7d3c80fba5235f9aff5bef8e165302bf2a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87646
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refactors the code by eliminating unnecessary NULL pointer
checks for the `efi_bmp_image_header header` parameter in several
functions. The calling function `fsp_convert_bmp_to_gop_blt` already
verifies that the `header` pointer is not NULL before invoking these
functions, rendering these checks redundant. Similarly, checks for
`adjusted_x` and `adjusted_y` in `calculate_adj_height_width` have been
removed. This streamlines the code and reduces unnecessary operations.
Additionally, the `is_bmp_image_compressed` function has been simplified
for improved readability by directly returning the result of the
compression type comparison.
Change-Id: Ia8afcac0fb21633e379f5d8b9713ba6f8b92c1c8
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87616
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This reverts commit d263e0bd92.
Commit a7eb390796 ("mb/*/*/*.fmd: Start flash at 0") changed the FMAP
to always begin at 0 and not at the x86 MMIO address where it gets
mapped, so the commit reverted by this patch isn't needed any more after
the FMAP change has landed.
Change-Id: I6d866ce3a3395f9fe70c47892a224e89ff89b20e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
amdfwtool is always setting BIOS relative as address_mode for the APOB
NV binary. So instead of giving amdfwtool a memory address we should
give it a flash relative address.
Change-Id: I4596902ca6c9880217247ce6fe96fcb516aec54d
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
1. frequency changes to 366 kHz from 457 kHz
2. tHIGH changes to 0.8 us from 0.514 us
3. tSU:STA changes to 0.68 us from 0.56 us
BUG=b:417375114
BRANCH=firmware-rex-15709.B
TEST=1.emerge-rex coreboot chromeos-bootimage
2.EA is measured and verified by HW
Change-Id: I996885a9acf2eea7f49ecf2fcd4f7d3fda842c8e
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
According to the HW schematics, GPP_A14 should be set as USB_OC1
for the A0 port, but it was found that the USB3_A0 port did not
match the configuration, so this has been corrected.
BUG=b:410481989
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I2fcf15ca008eca6c74f4020c3fa7af8863a56a00
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87637
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Perform early initialization of essential ChromeOS-specific
peripherals and GPIOs within the `bootblock_mainboard_init()`
function. This ensures critical communication paths and
hardware states are configured early in the boot process.
Specifically, this commit:
- Calls `setup_chromeos_gpios()` to configure general AP/EC
interrupts, and conditionally sets up GPIOs for the FPMCU
(reset, boot mode, power rails) and Soundwire amplifiers
(enable pins).
- Initializes the I2C bus for the H1/TPM via `i2c_init()`
when `CONFIG_I2C_TPM` is enabled.
- Initializes the SPI bus for the ChromeEC via `qup_spi_init()`
when `CONFIG_EC_GOOGLE_CHROMEEC` is enabled.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Ic29de4c1f48f33bd1ce6a4385bfc22fdef7ab911
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87642
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add IDs from the EDS, with a couple extras:
- eSPI: EDS says 0x7202, but our boards show 0x7702
- GT: Value changes between 0x7d51 and 0x7dd1 based on DIMMs installed
Change-Id: I8430914edd02954cbb38592bff896733b01c735d
Ref: Intel Arrow Lake-H/U EDS, Volume 1 (#777369, rev 2.0)
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87131
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The Lemur Pro 13 (lemp13) is an Intel Meteor Lake-U based board.
There are 2 variants to differentiate which keyboard design the unit
uses, as they require different EC firmware.
Change-Id: Icac8c7dafd6371881622d797f399f8ddbe13cbce
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Align with Cannon Lake SoCs and make it clear that SMRAM is
and should always be locked. This is cleanup, since Skylake's
Kconfig selects HAVE_SMI_HANDLER.
Change-Id: I136c69ad831d9e16d5034d6e488ee061c9b887f5
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Nuvoton NCT6779D has an undocumented GPIOE# functionality similar
to that found in NCT6791D. Its latched status can be read from
LDN B register 0xfb. Add it to the roster of dumped registers to
help development.
Change-Id: Id050b8efde855dec8099f1ac35307f7d372ae499
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Since commit bb66d07d41
"soc/amd/common: Always use genoa SPI MMAP driver" the ROM size can be
actually be greater than 16MiB on all AMD platforms without seeing a
boot failure. Since still only 16MiB of the SPI flash are MMAPed,
the FMAP should not be extended, and if so should only contain non x86
firmwares in the upper 16MiB of flash.
Now that common code supports ROM_SIZE greater than 16MiB select the
correct BOARD_ROMSIZE_KB for each mainboard.
Change-Id: Icdce01bddbc4873ba42ceddcda6d9075f5a42914
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Perform comprehensive peripheral initialization across romstage
and ramstage for the Bluey mainboard. This brings up essential
ChromeOS components and manages their power/reset sequences.
Key changes include:
- FPMCU Power & Reset:
- Enable `GPIO_EN_FP_RAILS` in romstage for power rail
stabilization (conditional on SPI fingerprint).
- Deassert `GPIO_FP_RST_L` in ramstage once FPMCU power is stable.
- QUPv3/GPI Peripherals:
- Load GSI (Generic Software Interface) firmware for
QUP_0/1/2_GSI_BASE.
- Initialize various QUPv3 Serial Engines (SE) in ramstage:
- UART for console (if not `CONFIG_CONSOLE_SERIAL`).
- I2C for Touch and Trackpad controllers.
- UART for Bluetooth module.
- SPI for the Fingerprint module (conditional on Kconfig).
- Display Initialization: Add a placeholder function `display_startup()`
in ramstage.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Iaa800e89eb521dc9d7b0a01984ca07b46a2a29d6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87643
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The bootblock requires early initialization of the Quad-SPI (QSPI)
controller to enable reading firmware from flash memory.
This commit adds calls to `quadspi_init()` with a 50 MHz bus clock
and `qupv3_fw_init()` within `bootblock_soc_init()`. This ensures
that the essential hardware for flash access and related QUPv3
functions are properly configured during the boot process.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Ia32114527f4b7cbabef1c1f8b7ad6d2d4b71c1f8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: mukesh.savaliya
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add audio and display bus protection release functions to enable audio
and display subsystems. These functions should be called after
mtcmos_audio_power_on() and mtcmos_display_power_on() respectively.
BUG=b:379008996
BRANCH=none
TEST=build pass and driver init ok.
Signed-off-by: Irving-CH.lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: Idb9d6e7b3adac275ccbcb71e22126eed88149d0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add flow of checking RTC unlock protection state after RTC protection
unlock sequence. On failure, retry this flow several times.
Additionally, change the time of CBUSY maximum timeout to 1 second.
BRANCH=rauru
BUG=b:392197855
TEST=emerge-rauru coreboot chromeos-bootimage, when suspend/warmboot/
coldboot, RTC boots and works normally.
After 15 tests, the boot time will increase by approximately 1.3ms from
890.508ms to 891.832ms
Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Change-Id: Id4d537d9c60dc7520c446f1816ef95f9f1e0ff80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87638
Reviewed-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the MAINTAINERS file to reflect active
maintenance for the Google Bluey mainboard and Qualcomm SOCs.
Specifically:
- A new section `GOOGLE BLUEY MAINBOARDS` is added, assigning
Subrata Banik and Kapil Porwal as maintainers for
`src/mainboard/google/bluey/`. This is for the newly
supported Bluey platform.
- A new section `QUALCOMM SOCS` is added, assigning Subrata
Banik and Kapil Porwal as maintainers for `src/soc/qualcomm/`.
Consequently, `src/soc/qualcomm/` is removed from the
`ORPHANED ARM SOCS` section. This establishes active support
for Qualcomm SOCs within coreboot.
Change-Id: I355fcf7a7c6c865a1cc3c405d5f8d03747b2d9fc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Use an array instead of a variable as suggested by the TODO, so we can
remove the shellcheck disable and fix the warning.
Change-Id: I5e872ebe350f339b932a711fe7f6a68743f002ed
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Increment the version number for the current changes.
Change-Id: Iec94067e34292df3b85744a820ace4aa198a6322
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This fixes the shellcheck warnings about declaring and using local
variables at the same time.
Change-Id: Ia16911c9ea0a1b32c3480a93ca0e53a409e80d22
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87373
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Shellcheck warns that the interrupt() function is unreachable, but it's
set to run on CTL-C. Disable the warning.
Change-Id: I0b850573964c732b1a3875dfdc7c1f0d406bac1a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87371
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While not always necessary, for consistency, use the ${} around all
variables.
Change-Id: I53fdddfd41e8aaa062bee73f441c5a816282c8ed
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Abuild used a mix of 'function funcname' and 'funcname()`. This
standardizes them all to use the 'funcname()' format. While they do
the same thing, we should be consistent across the file, and the
'funcname()' syntax is generally preferred.
Change-Id: I7530aa41b6413f0d5febe3d8a0db4a98113e1448
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Abuild used a mix of echo and printf. This updates them all to printf,
which is generally safer, especially when printing variable content
that might contain special characters or start with '-'.
Change-Id: Ib7f35fbaaffe8a85e2b9a1d7c0b8e04ffe0e9901
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The [[...]] form is generally recommended as it's more robust and
handles edge cases better (e.g., word splitting, pathname expansion).
Change-Id: I74189c25f0e602a4359272033c6725494a0f487f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87367
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
