Lastbus is a bus debug tool. When the bus hangs, the bus transmission
information before resetting will be recorded. The watchdog cannot
clear it and it will be printed out on the serial console for bus
hanging analysis. On MT8189, this feature is enabled by using the
common driver lastbusv2.
BUG=b:379008996
BRANCH=skywalker
TEST=When detected bus timeout, lastbus show:
debug_ctrl_ao_INFRA_AO 0x10023000 43
3a8a4f33
a8a48000
00080003
13018200
af99e400
0003fc90
00001104
0009c7e1
30c00033
00000001
00000003
00003294
003c00a3
019f9ccf
00000000
00200000
f007fffe
0000001f
0e800000
80143800
070c2002
ff9215de
001f9215
00009860
00000033
60000000
3a2e4919
000150c5
00000026
01416600
81438640
00000000
d6450001
0000000c
818b1501
00000540
80000000
fff70001
fff00000
fe00011e
000001ff
11040003
00004e67
timestamp: 0x22c18b05c
Signed-off-by: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Change-Id: I8e0d8aa925e413459044737ffe4ef142fca8d627
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit adds a new function, disable_slow_battery_charging, to
disable charging on the Bluey mainboard. This function writes a disable
command to the SMBUS chargers, turning off the charging process.
Additionally, this patch makes the following changes to support this
new functionality:
- The charging.c file is now compiled in both the romstage and
ramstage phases.
- The new disable_slow_battery_charging function is declared in
board.h.
- A new charging_status enum is introduced to clearly define the
charging states.
These changes ensure that the system can now properly control charging,
allowing it to be disabled when necessary.
BUG=b:439819922
TEST=Able to build and boot google/quenbi.
Change-Id: Ic0c59e0509889e6d166becf76279718b853021cc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89022
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch isolates all charging-related functionality, including
enabling and disabling charging and reading SPMI registers, into a new
dedicated file, charging.c. This improves code organization and
readability by separating concerns, making the codebase easier to
maintain.
Additionally, `enable_battery_charging` is renamed to
`enable_slow_battery_charging` to explicitly state the maximum current
is 1A. The charging enablement logic is also moved to occur before
the AOP firmware is loaded.
TEST=Able to build and boot google/quenbi.
Change-Id: Ieb374cb34814e8eab8dc2ad6f5fb435190167bc7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89021
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SPMI (System Power Management Interface) driver is necessary
for power management functionalities on the Qualcomm x1p42100 SoC.
This commit adds spmi.c to the ramstage-y list in the Makefile.mk,
ensuring that the SPMI driver is compiled and available during the
ramstage of the coreboot execution.
TEST=Able to build and boot google/quenbi.
Change-Id: Iba0a423e4a25d7ec9c55e24a1463a4fd4c53cc4f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
On warm reboot the PWR LED isn't automatically turned on by the EC.
Turn it on in the ramstage code, which allows to see when the reboot
has happened.
TEST=PWR LED is on after warm reboot on Lenovo X220.
Change-Id: Ia5fe3a52a6be622785c9588a94242ac0de0e19fa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The EC doesn't care about POST codes send to port 80h and there's
no POST code display on the laptops, thus disable POST codes at all.
TEST=Lenovo X220 still boots.
Change-Id: Idf666796d3cbb504c6e68d84521359d7e2fe98d0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88999
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There is an issue with headset detection on Soundwire audio codec.
Specifically, if the audio is not active (playback/capture is not
ongoing), then 3.5 mm headset detection fails. There is a fix for
Francka (PTL design). Similar implementation is needed for Fatcat.
Port commit a23be7a6fe (mb/google/fatcat/var/francka: Disable ALC721 &
ALC722 clock stop support to francka. This allows the flag to be
overridden via devicetree, instead of relying on the default value in
alc711_slave. It helps fix the missing event issue when plugging or
unplugging the 3.5mm headphone jack.)
BUG=NONE
TEST=After boot to OS, verified headphone detection working using
"getevent" command. Seeing headset jack detected in output:
add device 3: /dev/input/event7
name: "sof-soundwire Headset Jack"
Change-Id: I717f31f8d492bd0b2523c77b7492e46f50de991e
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88986
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
When get_us_since_boot() is called in pre-ram stages on x86 init
the TSC frequency. The TSC frequency is necessary to calculate
the time spent since boot.
When get_us_since_boot() is not used in pre-ram stages the function
timestamp_tick_freq_mhz() will also be dropped by the linker, thus
there's no code size increase for common code.
Will be used in the following commit in pre-ram stages.
Change-Id: I7fd9eeadf3063a629dd589498fcb957b9bd66536
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88793
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Check if CPU has been replaced before doing ram init. When it
has been replaced disable MRC cache and do a full memory training.
Also use get_us_since_boot() to skip waiting additional 50msec
when not necessary. Setting up NEM in bootblock is so slow that
50msec might already have passed.
Before:
940:waiting for ME acknowledgment of raminit 116,514 (62,804)
After:
940:waiting for ME acknowledgment of raminit 68,708 (7,211)
Boots 48msec faster than before.
Change-Id: I2d9729792c3546dc9bf23192c42619cd7d639d1c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88794
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Generate RAM ID for MT62F512M32D1DS-023 WT:E
DRAM Part Name ID to assign
MT62F512M32D1DS-023 WT:E 7 (0111)
BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I6786bff4a03179e3f682ade57d795a449df14bbc
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88925
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because the machine shows circle icon instead of G icon in 'Setting'
->'Device'->'View keyboard shortcuts'.
So add MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD to enable G icon.
BUG=b:442310345
BRANCH=none
TEST= Build and boot to OS and enter 'Setting'->'Device'
->'View keyboard shortcuts' to see G icon.
Change-Id: I77e2ce1556ded97c4d146b3e12f751958f31db80
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This makes the code easier to follow.
Change-Id: I5a4b7fe99875a1addf611f569990ff9a3beda3ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74800
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only 3 bytes should be used for the reset vector and it looks like
modern tooling has no problem with using a regular relative jump
instruction.
TESTED: Qemu Q35 still boots fine.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie371000c60d66c032a8dcccb98e7627df09d3aa4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Disable Enhanced Intel SpeedStep Technology (EIST) to prevent
OS-controlled P-state transitions. This improves consistent CPU
frequency bevahior across all cores, which is critical for real-time
applictaions requiring deterministic performance.
The existing devicetree parameter 'eist_enable' only configures the
IA32_MISC_ENABLE register but does not affect the FSP-S parameter
'Eist'. This results in FSP re-enabling EIST during silicon
initialization, overriding the register setting.
Override the FSP-S 'Eist' parameter at mainboard level rather than
fixing it in SoC code, since devicetree parameters default to 0 when
unset and would disable EIST on boards that rely on FSP defaults.
Change-Id: Ic83246d88607a8ed0c9815e306934bcf0bf8f016
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88965
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable S0ix power states at baseboard level.
TEST=Booted into linux and verified S0ix is disabled:
- FADT Low Power S0 Idle (V5) = 0
Change-Id: I34243137c8b06efa476dda74763d358f88bfe6a5
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88956
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add scan_bus operation to fast_spi device operations to enable
discovery of statically defined child devices.
This allows device drivers such as drivers/pc80/tpm that are
physically connected to the fast_spi bus to be properly
enumerated and initialized during device tree scanning.
Without this change, child devices defined in devicetree under
fast_spi would not be discovered, preventing proper driver
binding and initialization.
Example devicetree configuration:
```
device ref fast_spi on
chip drivers/pc80/tpm # SPI TPM header
device pnp 0c31.0 on end
end
end
```
Without a .scan_bus hook in fast_spi_dev_ops, coreboot's
BS_DEV_ENUMERATE phase never creates the pnp 0c31.0 device. As a
result, in BS_DEV_RESOURCES you see, that the device PNP 0c31.0
is missing its function "read_resources":
```
(in BS_DEV_ENUMERATE)
[DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 11 msecs
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 1510 msecs
[SPEW ] scan_static_bus for Root Device done
... (in BS_DEV_RESOURCES)
[SPEW ] PCI: 00:00:1f.5 read_resources segment group 0 bus 0
[ERROR] PNP: 0c31.0 missing read_resources
[SPEW ] PCI: 00:00:1f.5 read_resources segment group 0 bus 0 done
[SPEW ] DOMAIN: 00000000 read_resources segment group 0 bus 0 done
[SPEW ] Root Device read_resources segment group 0 bus 0 done
[INFO ] Done reading resources.
```
With the implementation of scan_bus, the log shows that the resources
are allocated correctly:
```
(in BS_DEV_ENUMERATE)
[DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 11 msecs
[DEBUG] PCI: 00:00:1f.5 scanning...
[SPEW ] scan_static_bus for PCI: 00:00:1f.5
[DEBUG] PNP: 0c31.0 enabled
[SPEW ] scan_static_bus for PCI: 00:00:1f.5 done
[DEBUG] scan_bus: bus PCI: 00:00:1f.5 finished in 14 msecs
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 1536 msecs
[SPEW ] scan_static_bus for Root Device done
... (in BS_DEV_RESOURCES)
[SPEW ] PCI: 00:00:1f.5 read_resources segment group 0 bus 0
[SPEW ] dev: PNP: 0c31.0, index: 0x0, base: 0xfed40000, size: 0x5000
[SPEW ] PCI: 00:00:1f.5 read_resources segment group 0 bus 0 done
[SPEW ] DOMAIN: 00000000 read_resources segment group 0 bus 0 done
[SPEW ] Root Device read_resources segment group 0 bus 0 done
[INFO ] Done reading resources.
```
TEST=Verified on Siemens mc_rpl1 mainboard. TPM device properly
enumerated with scan_bus implementation.
Change-Id: I4049d2d3cd5132362a7efd551dc9dd78cd24b9eb
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88966
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Disable DPTF for mc_rpl platform. In this context, the DPTF
configuration is removed as well. DPTF is deactivated to improve
realtime performance.
Change-Id: I5f9c2d1d82e9c18eafb9761df87a0709bded5964
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This file contains functions related to PCIe and SMM, and so it's
needed by bootblock and ramstage, and possibly romstage. It's not needed
by SMM, and in a follow-up, the SMI handler will define `smm_region`,
causing a function redefinition error.
As this file isn't needed in SMM, and the SMI handler's function
will work for this board too, as it works for all silicon (it returns
values populated during ramstage, by board/silicon implementations
of the function), drop this compilation unit from SMM.
Change-Id: I0195e7d42b0669d675879fb4d2596aa4607095b9
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88995
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PcieRpLtrEnable[] is a boolean, so use true false.
Change-Id: I3ccc64d7bb1a756efe8fc109c51c029a5483c316
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Increase WAIT_AUX_READY_TIME_MS from 1 ms to 3 ms fix a 20s timeout bug
on Google/Cherry/Tomato and possibly other MediaTek Chromebooks
introduced in commit 6ba2df9be5 (soc/mediatek/common: Use polling to
reduce eDP HPD wait time).
Change-Id: I6f41c3733e67c85e4aea3ce3b641a98cad94715c
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88991
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
For following Mitac Computing platforms:
sc513g6 and r520g6sb
TEST=Build and boot on Mitac Computing/sc513g6 platform
TEST=Build and boot on Mitac Computing/r520g6sb platform
Change-Id: I57b82e8e836e3ee798c026d3aa43fb8ab969e2c6
Signed-off-by: Schumi Chu <schumi.chu@mitaccomputing.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
FSP sets the MemoryType to 0x2 (MEMORY_TYPE_UNKNOWN) when a DIMM is not
present in a given slot, so skip parsing of any DMI records with that
type set.
TEST=build/boot out-of-tree Starlabs Cezanne-based board with a single
sodimm installed, verify the DMI record for the empty slot is not
parsed/inserted into the SMBIOS tables.
Change-Id: I683c7bf65cc261b6a4fc4cb74e7b4b5f96283f61
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88974
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows the mainboard code to change FSP-M parameters depending on
parameters that are only known at run time and not at build time.
Mirrors change previous done for Mendocino and newer SoCs.
Change-Id: I6790648da3724a06a127c1cef939366588668440
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Add a Kconfig to enable mainboards to select SERIRQ_CONTINUOUS_MODE,
which will be used by a to-be-added Cezanne-based Starlabs Starbook
variant in a subsequent commit.
Change-Id: Ia4da699e836e8e3ca408b4b5744320723e17ca62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
According to the datasheet and the LCD team’s response, increase Touch
IC enable delay time to resolve touch failure after resume.
BUG=b:441010546
TEST=Checked the waveform and suspend stress test, both checked OK.
Meet seconds_system_resume < 0.5 sec, boot time < 1.3 sec.
Change-Id: I778fd79f7bad3ad1873880b7412c0c49dcb40b1f
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This change disables the C1E (Enhanced Halt State) power saving feature
by clearing bit 1 in the MSR_POWER_CTL register. Disabling C1E prevents
the processor from automatically transitioning to a lower
voltage/frequency when all cores are halted, improving deterministic
behaviour.
For this platform, disabling C1E is always required, so the direct MSR
approach avoids FSP reliability issues and configuration complexity
that would come with using the existing devicetree "enable_c1e"
parameter.
TEST=Booted into OS and verified register MSR_POWER_CTL Bit 1 cleared:
- Used rdmsr tool: rdmsr 0x1FC showed bit 1 = 0
- Confirmed across all CPU cores
Change-Id: If076f0bb42f3a0d4b8f895703e88eaf145e4a762
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88964
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Remove unused implementation files and declarations:
- Delete ramstage.c containing DPTF power limit configuration
- Remove corresponding ramstage.c reference from Makefile.mk
- Remove unused ADL board ID enumeration in variants.h
- Remove cpu_power_limits structure and variant_update_power_limits()
- Remove variant_devtree_update() function and its weak implementation
The removed code was related to device tree updates and power limit
configurations that are not used by this mainboard.
Change-Id: I1b1c742a4b62022b91de8215d30a4df4f8cf68f0
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88962
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the CPU power limits configuration at the variant level to use 28W
for PL1, PL2. Set PL4 to 64W. This ensures consistent thermal
performance and power management behaviour.
Change-Id: I355f12ad66e9682f3d50356028baea01b42bffa3
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88961
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the moonstone variant of the fatcat reference board by copying
the kinmen files to a new directory named for the variant.
BUG=b:441010542
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_MOONSTONE
2. Run part_id_gen tool without any errors
Change-Id: Iad11c892270f6abc53dee12366691a8c987879f0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88978
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
smmstoretool is effectively a UEFI variable store writing tool, with
a specific emphasis on the SMMSTORE backend implementation.
However, it could also support other backends. Since it's typical for
the variable store to be `n / 2 - 1` blocks, but not typical how large
each block should be, allow this to be overridden on the command line.
This is necessary because in EDK2, the module producing the firmware
volume block protocol, the backend, will initialise a HOB or set PCDs to
indicate the size of the store to the rest of the stack, and an
assertion will be hit if the store has been preseeded by smmstoretool
using differently-sized blocks.
For example, `make CFLAGS=-DSMM_BLOCK_SIZE=8192` builds this for a
firmware volume block protocol implementation with 8K blocks.
Change-Id: I08b78cfb0b591641f09fcf86f40dd31e6b6c9b30
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Call to abort() in die() causes many tools to assume that the cbmem util
crashed even in case of just incorrect parameters. Changing it to
exit(1) allows for easier error handling by just getting the exit code
instead of having to handle SIGABRT.
Change-Id: Ic59e3479dcbe090a43878bf773409781729146c8
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some legacy devices need to have the master bit set in the PCI config
due to old drivers not setting it correctly. Set the master bit if the
feature is enabled via Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE.
This implementation is similar to the approach used in an earlier
Siemens platform, as implemented in commit 78ec750610
("mb/siemens/mc_ehl: Enable master bit in PCI config space if allowed").
TEST=Confirmed bus master enabled via lspci after boot.
Change-Id: I6d358ba7147860fd1383abe667a7006d9a30d542
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88963
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable Intel Turbo Boost on this platform as a first step toward
consistent frequency behavior. This platform requires deterministic
performance characteristics rather than dynamic frequency scaling.
TEST=Boot into OS, read MSR 0x1A0 (IA32_MISC_ENABLE) and verify that bit
38 (Turbo Disable) is set.
Change-Id: I6e89cdaaa56b5e5c70461ac67159c0fc3975a429
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
One of my previous commits attempted to simplify azalia_codec_init(),
but resulted in illogical code which also introduced a bug in certain
cases.
To summarize, codec_is_operative() tells the controller to get the
vendor ID of a specific codec. While doing so, this also checks how the
controller and codec respond to see if they are functioning. However, we
read the response in azalia_codec_init(). Therefore, these functions
must be called sequentially in order to initialize the codecs correctly.
In certain cases, we would attempt to read the response without
requesting the vendor ID in the first place. This possibly caused
these verbs to not get loaded at all.
These are the areas affected by the bug:
- northbridge/intel/haswell/minihd.c
- soc/intel/broadwell/minihd.c
TEST=Verbs were loaded on HP ProBook 450 G3
Fixes: 516d05f43d ("device/azalia: Separate codec checking and initialization")
Change-Id: I82ada9e6eca0539b854b5bc61f6f7a88ffd1cdc5
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88918
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a purely cosmetic change to make things slightly more easier to
read. We also only add the IDs which are actively used in the codebase.
TEST=Timeless build produces identical binaries
Change-Id: I4ec0a570020059c85768bab913dff1ba1977e9f9
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88917
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Set the active core configuration for the processor on this variant to
use 4 P-cores and 0 E-cores. This ensures that only the performance
cores are enabled, which matches the intended use case for this specific
board variant.
Change-Id: If79b13fea16bcd369feb438aab4ab11dd63d4fab
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88958
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the CPU does not control any fans and the mainboard does not
implement a charger, remove all unnecessary DPTF UPDs. DPTF will be used
for limitting PL1 and PL2 in the future.
Change-Id: I22e1167cb2986f5c56ff6085236792adbb9a19cc
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88954
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board does only use SATA Port 0 and SATA Port 1. The rest is
disabled. In addition, power management features like DevSlp and
Aggressive Link Power management are not supported on this motherboard
and are deactivated accordingly.
TEST=Verified SATA config: `dmesg | grep -i "sata link"` shows ports
0-1 active at 3.0 Gbps (Gen2 limit).
Change-Id: I4567328c25f195fac8edc02518a6a812922f48e5
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
