Add the new memory support: Hynix H58G56CK8BX146
BUG=b:444335746
BRANCH=firmware-brya-14505.B
TEST=Run part_id_gen tool and check the generated files.
Change-Id: Id473adafffc1dabcb8f8e9a1f548966a0ba5a334
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89147
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the parade
touchscreen (PRT3406) device, connected to I2C bus 24.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:431660019
TEST=emerge-nissa coreboot and parade touchscreen can work well
Change-Id: Iaaf740032de973461b616e186ac628436cbbc2a5
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
BUG=b:440996061
TEST=Ensure that pipe/utmi clocks are ON and check
port link status to confirm USB connect.
Change-Id: If0997ecb43eb5f687f1416abe42764fa31b1eaf5
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support for HS-PHY/SS-PHY and DWC3 USB controllers
for USB Type A Host support.
TEST = Ensure that pipe/utmi clocks are ON and check
port link status to confirm USB connect.
Change-Id: Ife08801062da5a8f87491b020b3828c246aadea8
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89132
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the memory parts: H58G66CK8BX147 (Hynix) in mem_parts_used.txt
,and generate SPD id for the parts.
BUG=none
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I485d8f947b6d8efc5b43ea1ddf1e4187eb4cf2bb
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit adds support for logging Bluetooth device wake events in the
Pantherlake platform. It improves visibility into wake events triggered
by Bluetooth devices, which is crucial for debugging and power
management analysis.
Change-Id: I36bb08075e79ab3151cfdaf41ace2121aaac0973
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89057
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a new constant, ELOG_WAKE_SOURCE_PME_BLUETOOTH,
with the value 0x31 to represent Bluetooth as a wake source in the ELOG
event data structure. This change facilitates diagnostics and
event logging related to Bluetooth activity.
The cbfstool eventlog has been updated to include "PME - BLUETOOTH" in
the wake source types for event data printing.
Change-Id: Ib628502ddcccb4a781394a39b2aee6efa05ecf84
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
The header guard comment in the chip.h file was incorrect, using
_GENERIC_WIFI_H_ instead of the correct _WIFI_GENERIC_H_. This
commit corrects the typo to ensure consistency.
Change-Id: I00a93e811608ddf449065bc92441648f7332fc4b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89055
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Add support for USB controller, PHY and NOC clocks.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Verify the boot process on the X1P42100 by creating an
image.serial.bin. After booting, confirm that the USB clocks are
on by inspecting the Clock Branch Control Register (CBCR) for
each clock. The status is indicated by BIT31, where a low value
means the clock is on.
Change-Id: Ic78e75c2c9963311530172d802aabb03f540060c
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
When CONFIG_SSE is enabled use the "prefetchnta" instruction to load
the next chunk of data into the CPU cache. This only works when the
input stream is covered by an MTRR. In case the input stream is read
from the SPI ROM MMIO area it allows to keep the SPI controller
busy fetching new data, which is automatically placed into the CPU
cache, resulting in less I/O wait on the CPU side and faster
decompression.
When the input stream is not cachable the prefetch instruction has no
effect.
The SPI interfaces on the tested device runs at 100Mbit/s and the
Sandy Bridge mobile CPU has quite some work to do decompressing the
LZMA stream.
That gives the SPI controller enough time to preload data into the
cache.
The payload of 1100213 bytes is now read in 164msec, resulting in an
input bandwidth of 53MBit/s.
TEST=Booted on Lenovo X220 and used cbmem -t:
Before:
16:finished LZMA decompress (ignore for x86) 1,218,418 (210,054)
After:
16:finished LZMA decompress (ignore for x86) 1,170,949 (164,868)
Boots 46msec faster than before or 30% faster than before.
Change-Id: I3b2ed7fe0883f271553ecd1ab4191e4848ad0299
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Reorder Child Device mappings to prioritise EFP displays.
* Disable LFP1 as it is not present
Change-Id: Ib998bc6df5430d08f9ded4d1e84f5aaa57b8be3d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89097
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Reorder Child Device mappings to prioritise EFP displays.
* Disable EFP3 as it is not present
* Change eDP panel colour depth from 18-bit to 24-bit (8 bpc).
* Change POST brightness from 255 to 100.
* Change minimum brightness from 6 to 0.
* Change DPST aggresiveness to 6 to 2.
* Enable PSR
Change-Id: I895fc61dff120e0ae989f45b37c0c5cde3c5e2ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89095
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implements clock-based reset control via CLK_CTL_ARES_SHFT bit
in CBC, enabling reset of cores receiving CBC-generated clocks.
This is required for proper initialization of clocks needed for
subsystems like USB Type-A.
TEST: Verified on x1p42100 CRD by asserting CLK_ARES through CBC
register writes during USB Type-A enablement. Confirmed USB
enumeration and reset functionality serial console.
Change-Id: If878994eaa24a21061470f962a4883f29be5476f
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
:wq
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89102
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tracker is a debugging tool, including AP/INFRA tracker. When bus
timeout occurs, the system reboots and latches some values which could
be used for debug. On MT8189, this feature is enabled by using the
common driver tracker_v3.
BUG=b:379008996
BRANCH=skywalker
TEST=When detected bus timeout, tracker show:
**Dump systracker aw debug register start**
0x10208ae0:0x0:0x0:0x0:0x0:0x0
0x10208ae4:0x0:0x0:0x0:0x0:0x0
0x10208ae8:0x0:0x0:0x0:0x0:0x0
0x10208aec:0x0:0x0:0x0:0x0:0x0
0x10208af0:0x0:0x0:0x0:0x0:0x0
0x10208af4:0x0:0x0:0x0:0x0:0x0
0x10208af8:0xc0000020:0x5:0x101e80:0x0
0x10208afc:0xc0000120:0x100:0x1cc10040
**Dump systracker debug register end**
Signed-off-by: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Change-Id: Icb34c87adc099172abdfc9868ff8e30287e61be0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Extract the common parts of the mt8196 tracker driver into tracker_v3 to
improve code reusability.
BUG=b:379008996
BRANCH=skywalker
TEST=build passed.
Signed-off-by: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Change-Id: If71bffe03cd2c30a0e9b3057c39667c1c2fdcb62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Create the ojal variant of the ocelot reference board by copying the
ocelot files to a new directory named for the variant.
BUG=b:437459757
TEST=1. Build emerge-ocelot
2. Run part_id_gen tool without any errors
Change-Id: Ic2fc86d89facae21b9bed898ebe518d316d953da
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
`src/mainboard/*/common` doesn't need a Kconfig.name, so don't check
for one.
Change-Id: I6c69c174287f7f068e28ed9c33b9b5542c87ca60
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89051
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Adjust the linter to skip `common` directories, as a board_info.txt
serves no purpose there.
This also changes `sort | uniq` to `sort -u` for efficiency.
Change-Id: I29639d8b620bcd4f2f7032802f375d79ac391535
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89050
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Trying to read a firmware binary for Turin platform results in
"Invalid address(41400) or mode(0)" error. The utility does not
respect the address mode set by the directory header. The address
mode of th entries is valid only if the address mode of the directory
is equal to 2 or 3.
Check the address mode of the directory and use it for entries only
when its value is less than 2.
TEST=Successfuly parse vendor BIOS for Gigabyte MZ33-AR1.
Change-Id: I479bc846bfb334231fdc707274a8ac44b6c384d4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
According to AMD documentation, starting from Family 17h Models
00h-0Fh, the PSP on-chip boot loader reads the PSP directory pointer
from offset 0x14 in the Embedded Firmware structure, replacing the
previous offset 0x10.
The docs do not specify any special value indicating a change of
offset. Some AMI binaries use a zero address in this directory field,
which caused incorrect offset handling.
Change-Id: I67ab763d070a9580a8269b525b203c932c5b1b95
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Intel ifdtool can dump the Intel Firmware Descriptor, which is helpful
for debugging and inspecting firmware binaries. This utility lacked
similar functionality, so this patch introduces a `--dump` CLI option
to display decoded information from the embedded firmware header.
Currently, the output includes SPI frequency and read mode for various
AMD family models.
Change-Id: Ideb1076f1d580496dac293882007cfa4672d188b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Added support for new mainboard configurations, `ptlrvp_chromeec4es`
and `ptlrvp4es`, to the Intel PTLRVP platform. These configurations
extend the existing options for pre-production silicon of the
Panther Lake SoC.
BUG=none
TEST=Build with new configurations to ensure successful compilation and
correct feature selections.
Change-Id: I3f716ab71a97d02b1694858d966f8111f18adff3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88997
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the DRAM memory reservation range for TF-A
to align with the latest Bluey memory layout specifications.
TEST=Verified boot up on google/bluey.
Change-Id: Ifb67e591d0f3d28cd6b0856198b29af49c2aab4c
Signed-off-by: smadhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Remove presence detection flag for the DMIC and internal speakers.
While we're at it, fix the (non-functional) descriptive flags for
those two verbs as well. Remove unnecessary line continuations.
TEST=build/boot Win11 and Linux on Starbook KBL, verify speaker and
intermal mic working, as well as headphones/jack mic when plugged in.
Change-Id: I4d4a41736faac944b3165a56fe5846f24c20f549
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Remove presence detection flag for the DMIC and internal speakers.
While we're at it, fix the (non-functional) descriptive flags for
those two verbs as well. Remove unnecessary line continuations.
TEST=build/boot Win11 and Linux on Starbook ADL-N, verify speaker and
intermal mic working, as well as headphones/jack mic when plugged in.
Change-Id: If91c723b6a2fa145c640e06a21198c5ff30a34f2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Remove presence detection flag for the DMIC and internal speakers.
Update the subsystem ID to match that used by the AMI UEFI Firmware.
While we're at it, fix the (non-functional) descriptive flags for
those two verbs as well. Remove unnecessary line continuations.
TEST=build/boot Win11 and Linux on Starbook MTL, verify speaker and
intermal mic working, as well as headphones/jack mic when plugged in.
Change-Id: I7621a6b57fb525892e84d06470eab5a9bdd32065
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89042
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Raptor Lake FSP doesn't seem to honour not touching GPIOs, so set
this to avoid major issues such as the SSD not being recognised and
causing an indefinite hang.
Change-Id: I50edc788c7a4c6ee5a2d74aa76b9e33fb56ed15e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit adds a call to disable_slow_battery_charging() in the
lb_add_boot_mode function.
The logic ensures that charging is disabled if the system is booting in
a normal mode, where neither the LB_BOOT_MODE_LOW_BATTERY nor
LB_BOOT_MODE_OFFMODE_CHARGING flags are set.
This prevents unintended charging by the AP firmware when the device
is not in a low-battery state or booting from off-mode charging to
avoid battery unmanaged health related problem.
TEST=Able to build and boot google/quenbi.
Change-Id: I648dc72a35ad2773f803792248fa87351333828f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89023
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change implements `lb_add_boot_mode` for the `bluey` mainboard,
which adds the platform's boot mode information to the coreboot tables.
This is done by checking the EC (Embedded Controller) to determine if
the battery is below a critical threshold.
If the battery is critically low, the `LB_BOOT_MODE_LOW_BATTERY` flag
is set. This information is then passed to the payload, allowing it to
take specific actions, such as displaying a low-battery charging
screen.
TEST=Able to build and boot the `bluey` mainboard.
Change-Id: I473cec7645954e753e160467aa8b83b67b28ab76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88994
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a new coreboot table, CB_TAG_BOOT_MODE, to pass
platform boot mode information to the payload.
The new table defines flags for low-battery mode and off-mode charging,
which are essential for a payload to properly initialize the charger
driver.
The cb_parse_boot_mode function is added to read this information, and
the sysinfo_t structure is updated to store the parsed boot mode data.
This ensures that the payload can accurately determine the system's
power state at boot and payload operations are also in sync with the
boot firmware.
The following scenarios were tested and verified:
Scenario 1: Low-battery, no charger
- coreboot detects the low-battery state and performs an immediate
shutdown after displaying the low-battery splash screen.
Scenario 2: Low-battery, charger attached
- coreboot detects the low-battery state but continues booting because
a charger is present. The payload receives the low-battery
information (using the same source as coreboot) and correctly
initiates the charging process.
Scenario 3: Off-mode charging
- The system boots directly from an S5 state due to a charger being
plugged in. coreboot detects the off-mode state, skips the firmware
splash screen, and hands off control to the payload, which then
starts charging.
Scenario 4: Normal boot
- The system boots without any low-battery or off-mode conditions.
coreboot and the payload both detect a normal boot (using the same
information), bypass charging initialization, and proceed to boot the
operating system.
TEST=Able to build and boot on google/quenbi device and verify the boot
mode flag is correctly passed.
Change-Id: Iec25c6fdfcdc5ea7c397d2430ac7b545e1e068f2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89015
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change introduces `LB_TAG_BOOT_MODE` to the coreboot tables to
convey platform boot information to the payload. The new `lb_boot_mode`
struct uses `enum boot_mode_t` to specify whether the device is booting
in `normal mode`, `low-battery mode` or `off-mode charging`.
This is crucial for platforms where the Application Processor (AP)
manages the charging solution, as it provides the necessary context for
the payload's charger driver. By passing this data through the coreboot
table, we avoid redundant implementation and ensure consistent battery
and charging information is available across both coreboot and the
payload.
A new weak function, `lb_add_boot_mode`, is also introduced. This
function can be overridden by platforms that require this data to add
the boot mode information to the coreboot table.
TEST=Able to build and boot google/quenbi.
Change-Id: I5aea72c02b4d6c856e2504f4007de584c59ee89f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add the new memory support: Hynix H58G56CK8BX146
BUG=b:442335706
BRANCH=firmware-nissa-15217.B
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I8002c2c8e89882f4a705c7aae881544009f84e3b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit updates the PCIe root port numbering for Wildcat Lake
as per the revised EDS document. This update ensures alignment with
the PCIe root port architecture.
Current:
- Bus-Device-Function: 0h – 6h – 0h = Root Port 5
- Bus-Device-Function: 0h – 6h – 1h = Root Port 6
New:
- Bus-Device-Function: 0h – 6h – 0h = Root Port 9
- Bus-Device-Function: 0h – 6h – 1h = Root Port 10
This resolves the warning shown during PCIe enumeration in boot
logs.
References:
- Wildcat Lake Platform Message of the Week (#844458)
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:433687705
TEST=Boot the system with the updated firmware and verify that
below warning is not reported for the PCIe root ports:
"[WARN ] pcie_rp_original_idx: Unexpected root-port number '9' at
PCI: 00:06.0, ignoring."
Change-Id: Icf5e3ae3d008f8d79480959bef7b4768fb34b4a8
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
This commit updates the GPIO configuration for the Ocelot baseboard
variant. It changes the definition of `GPIO_SLP_S0_GATE` from
being not connected (0) to `GPP_C08`. This GPIO will be used as
an indicator for the EC.
References:
- Schematic version: schematic_1433518
BUG=b:440270606
TEST=Perform an S0ix sequence on the system and verify that the
power state is properly reported on the EC console.
Change-Id: I303322f233824e6980ff6078e62f66eba36203ed
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88875
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On older CPUs lacking ESRM (Enhanced Short Rep Mov) the rep stos
instructions are very slow. Since the MTRR that covers the SPI ROM
is disabled when setting up the NEM, the CPU will run with cache
disabled and is even slower.
The Sandy Bridge BWG and the Sandy Bridge UEFI reference code do not
disable the MTRR on the XiP, allowing the CPU to run at full speed
when setting up CAR. On UEFI the CAR is set up by touching each
cache-line once. It doesn't clear the CAR while doing so.
Do the same to speed up setting CAR:
- Invalidate the cache
- Enable the SPI ROM XiP MTRR
- Set CR0.CD=0
- Touch one spot in each cache-line
- Clear CAR after NEM has been set up
To ensure that the CAR MTRR area is 64-byte aligned add an ALIGN to
the linker script. All existing boards should use a 64-byte alignment
for CAR.
TEST=Booted on Lenovo X220 and measured with cbmem -t:
TODO: Test on platforms that have FSRM (Ivy Bridge and newer).
Before:
0:1st timestamp 1,083 (0)
11:start of bootblock 93,765 (92,681)
After:
0:1st timestamp 0
11:start of bootblock 24,027
Boots 69msec faster than before or about 4 times faster.
Change-Id: Ia8baef28fd736ef6bb02d8a100d752ac0392e1cf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88792
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Generated using update_ec_headers.sh [EC-DIR]
The original include/ec_commands.h version in the EC repo is:
9b00e297ee chipset: Add a host command to issue AP shutdown
The original include/ec_cmd_api.h version in the EC repo is:
0c77d31000 UCSI/PPM: Add ucsi_host_cmd tests
Change-Id: I9b27cdd946c2e20a996ef338ec57d08de4e26059
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
