This option existed to enable the MMIO eMMC DXE driver for AMD Picasso
boards with eMMC storage. The driver has been integrated into edk2 and
no longer requires guarding via a build-time option.
Remove the EDK2_PCO_MMIO_EMMC Kconfig symbol definition, associated
build logic, and the board-level select from google/zork.
TEST=build/boot AMD Picasso boards with edk2 payload.
Change-Id: I458a45ad752d88cc9252f2d8fe6b0e8ec054329d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This option existed because the inclusion of the UFS driver in edk2
needed to be guarded due to some issues on non-UFS equipped devices.
Those issues have been resolved in edk2, so the UFS driver does not
need guarding anymore.
Remove the EDK2_UFS_ENABLE Kconfig symbol definition, associated build
logic, and selection from google/brya baseboard.
TEST=build/boot UFS and non-UFS ChromeOS boards with edk2 payload.
Change-Id: I3f20d503de4a642ee3fbb175c267e1f5f7328c8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89857
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the default MrChromebox branch to uefipayload_2508.
This branch is rebased on the latest upstream edk tag
'edk2-stable202508', and includes a number of other improvements,
including memory safety fixes, improved support for eMMC on AMD
Picasso-based devices, improved UFS support for Alderlake-N based
devices, and a new driver supporting devices which use a Genesys
Logic GL97xx PCIe eMMC or SD card controller.
Change-Id: Id5d02da6396ce7ec7bfb7aaa90ebb234ec05020b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89856
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit adds a new Kconfig option to the `fatcat`
mainboard to enable VGA mode 12 support for early Sign of Life
(eSOL).
- This option, `FATCAT_VGA_MODE12_SUPPORT`, is dependent on
`FSP_UGOP_EARLY_SIGN_OF_LIFE`.
- It selects `ROMSTAGE_VGA` and `FSP_VGA_MODE12` to enable the
necessary VGA components.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: I3b9a433c7b3938b8cc17f44552b8463ee049e5c3
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89092
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit implements the configuration of VGA mode 12 in the
Intel Pantherlake SoC's romstage. It integrates the newly added
text rendering API to display user messages using a planar buffer
instead of the standard VGA message string.
The changes include:
- A call to `render_text_to_bitmap_buffer()` to draw the message
on the bitmap buffer.
- Determining the display orientation from the common SoC
configuration, with an override for a closed lid.
- Calculating and setting the correct position of the rendered
text in the VGA buffer.
- Duplicating the single-plane bitmap data to all required planes
for VGA mode 12.
- Setting the `VGA_INIT_CONTROL_MODE12` bit in the FSP-M UPD
to inform FSP to use the new mode.
- Implementing the `soc_set_vga_mode12_buffer()` API to set the
corresponding FSP-M UPD for VGA mode12 buffer address.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: Ic69fff0479020a31c7e6f0c52b4bdb25b1483bb9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit adds new Kconfig options and a code snippet to support
VGA mode 12 within the FSP (Firmware Support Package) 2.0. The
changes allow platforms to select VGA mode 12 and configure it.
The key features are:
- Introduces `FSP_VGA_MODE12` to enable VGA mode 12 support.
- A new `FSP_VGA_MODE12_BPP` option defines the bits per pixel,
defaulting to 4 for color mode.
- A bitmap buffer is allocated on the stack and supplied to FSP
based on the configured bits per pixel.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: Iaa3a64b7c8c735d8329b3596f4be315871bc7fa4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add 2 new timestamps for measuring the time to generate pKVM
deterministic random number generator seed in depthcharge.
First indicate when the generation has started and
a second when the setup is complete.
BUG=b:449097147
TEST=builds
Change-Id: I1bced5a331e4d10a1ec1c305b9b2a41d1e913579
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89872
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch fixes a number of rare edge cases in handling the precision
argument in printf. The existing printf implementation used 0 as the
sentinel value for "no precision provided", which makes sense for
integers (where 0 precision has the same effect as no precision, since
in both cases no extra zeroes will be added to the front). However, for
strings it can make an important difference, since callers may expect
that they can use `printf("%.*s", len, str)` to guarantee that `str`
doesn't get dereferenced when `len` is 0. Therefore, change the
implementation so that negative values are used to represent "no
precision provided", and 0 is a legitimate value.
print_string() also had the problem that it called strlen() on the
string before even evaluating the precision. That of course defeats the
purpose of the common "%.*s" pattern to access unterminated strings.
This patch fixes the problem.
Finally, this patch slightly modifies the behavior when printing a NULL
pointer as a string, to make sure width and precision values are still
taken into account in that case, and to change from `(NULL)` to `(null)`
to match the behavior in glibc.
Change-Id: I787c18e1d33006842cf758aeb87710f80f0e5a40
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89837
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable hardware-managed microphone privacy by setting the
PchHdaMicPrivacyMode FSP UPD to 1. This feature was enabled by
default in FSP previously but has since changed to disabled by
default, so now coreboot explicitly enables this as it is a desired
feature for Chrome platforms.
The hardware-managed microphone privacy feature allows the platform
to control the microphone mute state at the hardware level for
enhanced privacy.
TEST=Verify UPD value is set correctly and HW managed mic privacy is
working as expected.
Change-Id: I9a20bd129103aae35550104f6a7025484ef5e9c1
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88451
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
Modify touchpad device setting to enable the ELAN touchpad.
schematics: RUBY_EVT_0902_2112.pdf
Device i2c log:
[INFO ] \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
[INFO ] \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
[INFO ] \_SB.PCI0.I2C0.D04B: TI SPK AMP L at I2C: 00:4b
[INFO ] \_SB.PCI0.I2C0.D04C: TI SPK AMP R at I2C: 00:4c
[INFO ] \_SB.PCI0.I2C0.D04D: TI SPK AMP TL at I2C: 00:4d
[INFO ] \_SB.PCI0.I2C0.D04F: T1 SPK AMP TR at I2C: 00:4f
[INFO ] \_SB.PCI0.I2C3.TPMI: I2C TPM at I2C: 00:50
[INFO ] \_SB.PCI0.I2C4.H015: ELAN Touchpad at I2C: 00:15
[INFO ] \_SB.PCI0.I2C5.H014: Goodix Touchscreen at I2C: 00:14
[INFO ] \_SB.PCI0.RP01: Enable RTD3 for PCI: 00:00:1c.0 (Intel PCIe Runtime D3)
Changes:
hid : From PIXA2305 to ELAN2705
hid_desc_reg_offset : From 0x20 to 0x01
address : From 0x2C to 0x15
BUG=b:449901218
TEST=Build and boot to OS and use Elan touchpad module to verify the cursor works.
Change-Id: I11dcca5db5558af4cdd4b87a9b42519615839fef
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit removes the explicit CONFIG_HAVE_BMP_LOGO_COMPRESS_LZMA
definition from the Panther Lake Kconfig.
This local Kconfig setting, previously defaulted to 'n', is redundant
because the Panther Lake build now correctly inherits the intended
system-wide default, which is to use LZMA compression for the BMP
splash screen.
Removing this unnecessary Kconfig option simplifies the configuration
and results in a measured ~3ms reduction in boot time during the
firmware splash screen rendering phase on Panther Lake platforms.
w/o this patch:
```
963:returning from FspMultiPhaseSiInit 1,096,797 (102,937)
17:starting LZ4 decompress (ignore for x86) 1,111,606 (14,808)
18:finished LZ4 decompress (ignore for x86) 1,111,641 (34)
17:starting LZ4 decompress (ignore for x86) 1,119,857 (8,216)
18:finished LZ4 decompress (ignore for x86) 1,119,879 (21)
```
w/ this patch
```
963:returning from FspMultiPhaseSiInit 1,097,817 (103,211)
15:starting LZMA decompress (ignore for x86) 1,110,058 (12,241)
16:finished LZMA decompress (ignore for x86) 1,111,096 (1,037)
15:starting LZMA decompress (ignore for x86) 1,117,554 (6,458)
16:finished LZMA decompress (ignore for x86) 1,117,906 (352)
```
Change-Id: I64579e53c7f307d1430767da04a413f80016487f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Use defined constants from ec.h instead of hardcoded integer values
in all CFR enum definitions for improved readability and
maintainability.
Change-Id: I13b313d0c7a177fc689c3022256eb17125354599
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89881
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the "wireless" option enable or disable the USB Bluetooth along
with the wireless card.
Change-Id: I253b83ac3efb768e91dba424be4cec6a56bf53f8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89798
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For reasons currently unknown, using a level triggered interrupt for the
PS2 keyboard causes an IRQ storm under Windows when any key is pressed,
leading to audio distortion/dropouts. Work around this by using an edge
triggered interrupt instead.
BUG=none
TEST=build/boot Win11, Linux on google/skyrim (frostflow), verify kb
functionality, verify no IRQ storm or audio stutter/distortion under
Windows.
Change-Id: I6de426c5780b2f05571415e8e411e379de45b5bf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
When the mainboard is Bluey, the Kconfig options 'ARM64_HAS_SECURE_OS'
and 'ARM64_HAS_SECURE_OS_PAYLOAD' are selected to pack and load the
QTEE firmware as a CBFS payload type, since its memory regions are non-
contiguous across system IMEM and DDR.
TEST = Create an image.serial.bin incorporating QTEE firmware and
ensure it boots to OS on X1P42100.
Change-Id: Iaedfa25d574af8451a7bb9a4a35c557f4e09eee2
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89554
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a fw_config for touchscreen and non-touchscreen sku.
Based on the field to differentiat the touchscreen I2C port on/off
and GPIOs configuration.
BUG=none
TEST=Update the fw_config field and check the ap log:
ABSENCE = 0 ... without touchscreen i2c probing messages.
PRESENCE = 1 ... with touchscreen i2c probing messages.
Change-Id: I5f2cc0b0c37986240fbbeae3668ccc250748295d
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89851
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
commit 668ea970 ("commonlib/endian: Silence GCC -Warray-bounds false
positives") added `#pragma GCC diagnostic ignored "-Warray-bounds"` but
forgot to restore the diagnostic state at the end of the file.
Change-Id: I41b38758ce862490777ede63ff92d95d6ba21521
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89867
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change applies the same fix as coreboot change CB:89605 to the
kinmen variant. Without this change, headset jack detection won't work.
The original change 752d49a4ff was:
"mb/google/fatcat/var/moonstone: Disable RT721 clock stop support"
RT721 headset jack detection fails because the wakeup event is not
triggered during runtime suspend in D3 state. Disable the clock stop
to allow the bus driver to handle the wakeup process properly. The MIPI
Disco property is "mipi-sdw-simplified-clockstopprepare-sm-supported".
BUG=b:435094908
TEST=After plugging a headset, audio output is switched to it.
Change-Id: I468d949e1249548348493c070b4955c012ef7b4e
Signed-off-by: Norman Bintang <normanbt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89784
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Adds the abillity to use a custom u-boot repo and a custom branch.
Change-Id: I15df8a41d3d94ca0559abc964792035651b3d8b2
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89616
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apparently no one ever build this using UBOOT_MASTER, because it is
missing the "cd $(project_dir)" before git fetch.
I have also no idea what the git show was originally supposed to do.
So just remove them both and move on.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2f26660131ce91420a951fb33ac0eef89371745d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89615
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Add a new function google_chromeec_has_kbbacklight() to check if the EC
has keyboard backlight capability. The function first tries the EC
feature flag (EC_FEATURE_PWM_KEYB), falling back to a read test if
unavailable. The EC command ec_cmd_pwm_get_keyboard_backlight() returns
-1 if the device does not have a keyboard backlight.
This function will be used in subsequent commits to guard setting the
keyboard backlight at boot and the visiblity of a CFR option setting.
TEST=tested hooked up to a CFR option to set the keyboard backlight
at boot, with visibility controlled by backlight presence, on a
range of Chromebooks with and without keyboard backlight support.
Change-Id: I74daf7a63f06239d2ba3915221555af494a9340f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89827
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`ToString(byte x)` is undefined behavior per the ACPI spec, which
causes Windows to discard the battery device status entirely.
Fix this and improve performance of the BRSX method by using an array
to store the characters read, calling ToString() only once at the end.
TEST=build/boot Win11 and Linux on google/rex, verify battery status
reported properly under both OSes.
Change-Id: I4e5aea3b2763a3c4433abe95c3a41d218fcd06c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Set the GPE0 registers (DW0, DW1, and DW2) to configure General
Purpose Events (GPEs) for the Lapis variant. This configures
GPP_VGPIO, GPP_F, and GPP_E as the Tier-1 PMC GPIO groups.
This patch ensures the variant can override the default baseboard
(fatcat) GPE settings, which may not align with the variant's
(aka lapis) hardware.
BUG=b:414614106
TEST=Able to override PMC GPEs as per google/lapis configuration.
Change-Id: Icd191d5265619ebfbf7f8dabb39a91a6517dfbd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
Configure the Touch Host Controller (THC) devices 0 and 1 on the
Fatcat/Lapis variant to use HID over I2C mode.
This change explicitly sets the thc_mode[0] and thc_mode[1] registers
to THC_HID_I2C_MODE in overridetree.cb. This is necessary to correctly
initialize the THC for devices like touchpads or touchscreens that
communicate using this protocol.
BUG=b:455442712
TEST=Able to build and boot google/lapis with functional touchpad.
Change-Id: I7c9a62afab396cb38775eaa5e96f2dc7ed773216
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89818
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Touch Host Controller (THC) requires its dedicated VGPIO pins to
remain enabled as a General Purpose Event (GPE) source for the system
to wake up on touch events.
This change introduces override_tier_1_gpio_chip_config to explicitly
check the thc_wake_on_touch status for each enabled THC interface.
If any wake-on-touch functionality is active, the Tier-1 GPE
configuration (pmc_gpe0_dw0) is overridden to ensure the GPP_VGPIO
bank is included.
This guarantees that the VGPIO pins dedicated to THC are always
monitored as a wake source when required by the platform
configuration.
BUG=b:414614106
TEST=Able to build and boot google/fatcat.
Change-Id: Ia1165c167850f5d66a8c5a85e3ec64f80e7a40da
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89817
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add stop pin control for G2 touchscreen.
BUG=b:456578327
TEST=build and verified Touchscreen work normally.
Change-Id: I0581fffdc2ec16a1c36b2e716b0fae27bad465ee
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89813
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The pcie_speed_control_to_upd() helper function was only available in
aspm.c for PCH root port configuration. However, CPU root ports in
romstage also need to convert PCIE_SPEED_control enum values to FSP
UPD indices.
Move pcie_speed_control_to_upd() from aspm.c to pcie_helpers.c to
make it available in both romstage and ramstage. This allows both
PCH and CPU root port code to use the same conversion logic without
code duplication.
The helper handles the mapping between devicetree enum values and FSP
UPD values using the UPD_INDEX() macro (which subtracts 1):
- SPEED_DEFAULT (0) -> SPEED_AUTO (1) -> UPD_INDEX = 0
- SPEED_AUTO (1) -> UPD_INDEX = 0
- SPEED_GEN1 (2) -> UPD_INDEX = 1
- SPEED_GEN2 (3) -> UPD_INDEX = 2
- SPEED_GEN3 (4) -> UPD_INDEX = 3
- SPEED_GEN4 (5) -> UPD_INDEX = 4
This accounts for the fact that FSP expects 0-based indexing where
0 = Auto, 1 = Gen1, 2 = Gen2, etc.
TEST=Configured PCIE_SPEED_GEN2 for root port on mc_rpl1, booted and
verified with lspci -vv that device is limited to Gen2 speed
Change-Id: I0f70ad4da6f9f9e73b1c05648f0b206d5d61e07d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This is a more suitable place for these definitions as
it contains all other ECRAM offsets.
Change-Id: I12f52b7b27b24c49b6dfc3d4b8fa0718605d2d5f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89695
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the Moonstone Schematic Proto 2.0 design, disable
Thunderbolt support for TCSS_PORT0 on the MB and TCSS_PORT1
on the DB.
Schematic: Kinmen(ZDQ)_Proto2.0_Moonstone_1014.pdf
BUG＝none
TEST=emerge-fatcat coreboot
Change-Id: Ie9acb9d68234b2d8bfc9392cf89d581de8c54a08
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89819
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The left-up and right-up orientations were swapped. Fix it to align
with boot logo and depthcharge screen.
BUG=b:406725440
TEST=Verify all 4 panel orientation on Google/Felino.
Change-Id: Ib0d08d4b2aa697129d854c15e081c7765e542060
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Ensure FMAP_CBFS_BASE is aligned to 4k (0x1000) to match typical flash
sector boundaries. This allows flashrom to read/write only the COREBOOT
region using the --fmap layout option without extending the boundaries.
Previously, the COREBOOT region would start immediately after the FMAP
region (at FMAP_BASE + 0x200), which is not sector-aligned. Most flash
chips support a minimum 4k sector size, so flashrom would automatically
extend the region boundaries and emit a warning.
This eliminates warnings from flashrom such as:
Region [0x00c54000 - 0x00c541ff] is not sector aligned!
Extending end boundaries by 0x00000e00 bytes,
from 0x00c541ff -> 0x00c54fff
TEST=build/boot google/gladios, update using --fmap and verify no
warnings regarding region alignment.
Change-Id: Ie4963bbef546aa23364bb9c1c347c5eb5bfeaf8e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The generated build/fmap.fmd file was displaying region sizes and
offsets in a mix of decimal and hexadecimal formats, making it harder
to read and compare values. This change ensures all numeric values are
consistently printed in hexadecimal.
The conversion to hex is done in two places:
1. For conditional FMAP entries (MRC_CACHE, SMMSTORE, SPD_CACHE, VPD,
HSPHY_FW, CONSOLE), the _tohex conversion is applied at entry
definition time. This is necessary because these entries may be
empty when their respective CONFIG options are disabled, and the
conditional logic happens before the sed substitution.
2. For unconditional values (ROM_SIZE, BIOS_BASE, BIOS_SIZE,
FMAP_BASE, CBFS_BASE, CBFS_SIZE), the _tohex conversion is applied
directly in the sed command when generating fmap.fmd. This keeps
the base variables in decimal form for continued use in arithmetic
operations.
All internal calculations continue to use decimal values. Only the
final output strings that are written to fmap.fmd are converted to hex
format.
Before:
SI_BIOS@29032448 4521984 {
SMMSTORE@65536 0x40000
RW_SPD_CACHE@327680 4096
After:
SI_BIOS@0x1bb0000 0x450000 {
SMMSTORE@0x10000 0x40000
RW_SPD_CACHE@0x50000 0x1000
Change-Id: I48cc39b430943cb4923955b5e3d64ad6dd24a6cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89836
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Enable rp5 if the FW_CONFIG bits for WIFI are set to WIFI_PCIE_6 or
WIFI_PCIE_7.
BUG=b:444509417
TEST=emerge-ocelot coreboot chromeos-bootimage', flash ocelot and
verify CNVI and PCIe WiFi solutions are detected correctly.
Change-Id: I077bfc48a82c354d1011ef756aa6aa55bf6951cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The `EC_STARLABS_ADD_ITE_BIN` Kconfig option is only meaningful on
Star Labs boards with an ITE EC, i.e. those with `EC_STARLABS_ITE`
selected. So, add a "depends on" line so that the former option is
only visible on applicable boards.
TEST=`EC_STARLABS_ADD_ITE_BIN` no longer shows up for qemu-q35.
Change-Id: Ifb40d8b432d2abeadba2a970010dac126e4b7418
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
PCIe Root Port 5 uses both CLKSRC 1 and CLKSRC 2, but coreboot's
devicetree only allows configuring a single clock source per port. Add
a comment to document that CLKSRC 2 is implicitly used by the hardware.
Change-Id: I9b54d97fa5e4e4e80a58392a7592bab91e00824d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Expose the PchHdaMicPrivacyMode UPD parameter in the FSP-S
configuration structure for WildcatLake. This parameter controls
the HD Audio microphone privacy mode, allowing mainboards to
configure whether microphone privacy is hardware-managed,
firmware-managed, forced to mute, or disabled entirely.
TEST=Built WCL FSP successfully with this change.
Change-Id: If48c684aea09291715718a6e8fb400b9550aab61
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Update thermal design current (TDC) values for GT domain across
multiple PTL SKUs based on input from Power and Performance team.
BUG=none
TEST=Boot to OS on fatcat device and check performance.
Change-Id: I6333f8b5db8c7fc1739d0772d83bfe602a837a53
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89697
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Ma, Zhixing <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch to using `objdump -f`, which consistently prints the line
"file format <format>" across modern binutils versions, and extract
the architecture format from that output. This restores correct
toolchain detection on Ubuntu 25.10 and other systems with binutils
≥ 2.43, without breakng older versions.
Before:
DEBUG: obj_type:
/tmp/temp.rrDQ8i.o: file format elf64-x86-64
DEBUG: obj_arch:
After:
DEBUG: obj_type:
/tmp/temp.8GsK08.o: file format elf64-x86-64
architecture: i386:x86-64, flags 0x00000000:
start address 0x0000000000000000
DEBUG: obj_arch: elf64-x86-64
Change-Id: Ic09304f9e81580bbe1c0bb4910c0cc534d3d2816
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89643
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This reverts commit 8a2c04e04d.
Reason for revert: The hang is still present
Change-Id: Iba3c2b684cce3adefecd175d0ef09a5d051410ae
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89805
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
