Add DT, WLAN, WWLAN, TB and XGBE port descriptors
according to PI source package #67683 (NDA).
Change-Id: Iccc74fd03f6833112b370ba503d9d33033609c5b
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The parameter CPU isn't used, thus drop it.
Change-Id: Ie7f6179f0545f905463752e94243b438143d8234
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Update the default branch used for MrChromebox's edk2 fork from 2024-08
to 2025-02. This updated branch has been rebased on the latest upstream
stable tag (edk2-stable202502), and updates the EFI revocation database
used for SecureBoot. It also adds support for the CFR-based setup menu
and configuration management, and support for running OpROMs on
external dGPUs.
TEST=build/boot google boards link, panther, lulu, reef, ampton, akemi,
banshee, zork, dewatt, frostflow with edk2 payload selected.
Change-Id: I1f900d0e33e88d747547a1f5218445bb0cce4e4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87406
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Ensure all boards configure these two GPIOs to NF1.
Change-Id: Ie8a222bff349a427083adb1c4d7ca73a41de3095
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This patch adds Wildcat Lake-specific CPU and PCIe device IDs to the
header files and driver-specific code.
Reference:
Wildcat Lake Processor Prelim External Device IDs (820363)
BUG=b:394208231
TEST=Verified on Wildcat Lake Simulation Platform
Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87262
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new static function `disable_vr_settings_on_pantherlake_h()`
to disable Voltage Regulator (VR) settings when a Panther Lake H System
on Chip (SoC) is detected.
The existing VR configurations, introduced by commit d19dd192db
("mb/google/fatcat: Add PTL-U Fast VMode Voltage Regulator settings"),
are optimized for Panther Lake U SoC, which can cause performance issues
on Panther Lake H boards under stress due to the I_TRIP value being
lower than what the device could actually use. By disabling these
settings, the Firmware Support Package (FSP) falls back to default
values for the SoC, which are more suitable.
TEST=Observe the "Disabling VR settings on PTL-H" log during a boot test
on a Panther Lake H variant.
Change-Id: Ifc371212259fa724425158ad9ebadebd30c81705
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update gpio configuration to match ocelot schematic.
BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.
Change-Id: Id2e2eb9fdf008445124e99393fe4b192ccb27f5d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Update the FW_CONFIG to correspond to the Google Ocelot hardware SKUs
and remove code that is no longer needed due to the FW_CONFIG changes.
Removed support for AUDIO_ALC722_SNDW, AUDIO_MAX98360_ALC56821_I2S,
AUDIO_MAX98373_ALC5682_SNDW, TOUCHSCREEN_LPSS_I2C, UFC_MIPI, UFC_USB,
WFC_MIPI and WFC_USB.
Added support for AUDIO_ALC721_SNDW, DISPLAY_TOUCH_PRESENT, and
DISPLAY_NO_TOUCH_PRESENT.
BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.
Change-Id: I5fd7010230a3f17005f5ca395ffaca0724a615e9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I97d5d8b78cc9e5516dbfc64f81a925b1715b941b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I1c51e653a9e34bb7f5ac07bcae8481be269f83cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the IGD config options IgdDvmt50PreAlloc and ApertureSize to the
option API, so they can be configured at runtime without recompilation.
The Aperture size falls back to the FSP default value, so no change if
unconfigured.
Change-Id: Idad22ca79c10d575320b4360ec24c2019a837446
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Add an option variable 'me_disable' to control the visibility of the
HECI PCI device at runtime. Default to the Kconfig selection if not set.
Change-Id: I6e7c018115780c74f1662948ed8dad3e0559051a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add an option variable 'me_disable' to control the visibility of the
HECI PCI device at runtime. Default to the Kconfig selection if not set.
Change-Id: I12c4c9f062cb5904c2f9c05b333bf0ed81aba632
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87384
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Organize according to stage, alphabetize, and guard inclusion of
ChromeOS-specific code.
TEST=build/boot stumpy
Change-Id: Id6ea4e685ff3e098f6c619e1cab48a5a9320c29b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable support for managing system options via CFR, and select it by
default when using edk2 with SMMSTORE.
TEST=build/boot stumpy w/edk2 payload
Change-Id: I91166a3932931c04eae78065fec6b856aebc6f0b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Since CFR options require a backend to store the keys/values, select
DRIVERS_EFI_VARIABLE_STORE when edk2 is used as the payload and
SMMSTORE is enabled, so that boards only need to select
DRIVERS_OPTION_CFR in order to have a fully-functioning configuration
setup.
TEST=build samsung/stumpy with DRIVERS_OPTION_CFR selected and edk2
payload used.
Change-Id: Ib8565e4fefb1b3f05e58ab039be8ab0d1bc046f1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
DRIVERS_EFI_FW_INFO requires some Intel vendorcode headers which are
selected by default on FSP 2.x platforms, but not by earlier ones.
Select the oldest UDK binding for non-FSP 2.x boards, so that the
required headers are available, rather than depending on UDK_BASE
and requiring those boards to manually select the binding
Change-Id: I27ab64ab0c9d4d45cc09061f6f8c3725c24df706
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
DRIVERS_EFI_VARIABLE_STORE requires some Intel vendorcode headers which
are selected by default on FSP 2.x platforms, but not by earlier ones.
Select the oldest UDK binding for non-FSP 2.x boards, so that the
required headers are available, rather than depending on UDK_BASE
and requiring those boards to manually select the binding.
TEST=build samsung/stumpy with EFI variable store support, without
manually selecting UDK_2017_BINDING at the mainboard level.
Change-Id: I099d3cc7690a0faecfe32a8bc814766c67c63fbb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87408
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
TEST=build/boot samsung/stumpy with CFR options enabled.
Change-Id: Ia6906992deb948869ecfd8a5f6fc3883220811ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them.
Currently only one option for IGD UMA size, but others can be added
as needed.
Change-Id: I892ffcc74d36a266697cbc7ea3c8880db6b67f44
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: Id69295ae1708164b1afbafe5724e19bf13fc3963
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87393
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the IGD config options IgdDvmt50PreAlloc and ApertureSize to the
option API, so they can be configured at runtime without recompilation.
The Aperture size falls back to the FSP default value, so no change if
unconfigured.
Change-Id: Ic900cb7bdc6dc532aef0c0b51b32bf8308a8ae36
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87392
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I1684439755db9d8194ac5533513e65c9ba8f0768
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Per the documentation, mainboards should select
`DRIVERS_OPTION_CFR_ENABLED` vs `DRIVERS_OPTION_CFR`, since the latter
is meant to be user selectable.
Change-Id: Ica2980fb9a8c69cae48e235ebbd72e824c24e010
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Allow the power state after failure to be set using an option backend
if used, otherwise fall back to the Kconfig selection. This is a
noop for all it8772f boards unless they enable an option backend, in
which case that option setting is now functional, whereas before it
would have been ignored for the Kconfig selection.
TEST=build/boot google/panther with various power state after fail
Kconfig selections.
Change-Id: I1988d70fe27a287cd2cc91dbb905c243c24c816d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87383
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the programming of the power state after power failure to the ITE
EC common code, in order to unify and extend to other ITE SIO chips.
The implementations in the it8720f and it8728f are functionally
identical, so take the "best" style elements of both, using clear
variable names and defines for registers rather than magic values.
Change-Id: I4b7e9455e964320f35997fdf04a515b942e030c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I734262c8191bc217c721c0174d0f844755bc73a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79917
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the epic variant of the nissa reference board by copying
the template files to a new directory named for the variant.
This variant is a Nirul project,support TWL devices and select
BOARD_GOOGLE_BASEBOARD_NISSA.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H58G56AK6BX069 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
H9JCNNNBK3MLYR-N6E 0 (0000)
H9JCNNNCP3MLYR-N6E 3 (0011)
BUG=404301972
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_EPIC
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I09e5f3c28b95ae8ef318b7af1dd8634279345ce0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87041
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
With DRIVERS_EFI_UPDATE_CAPSULES enabled and when at least one capsule
was found, SMMSTORE SMI handler can use commands with the highest
bit (0x80) set to access the whole flash instead of just the SMMSTORE
region. The rest of the interface is identical to regular SMMSTORE v2
except for a new call to control full flash access.
The added call saves information about the availability of capsules in
SMM memory. The call is ignored when run more than once, meaning there
should be no way of enabling full flash handling after it was disabled
and vice versa. The call should always be made by the firmware to lock
further calls, so that an OS could not gain full flash access. This is
done on entry to BS_POST_DEVICE after capsules are obtained in
BS_DEV_INIT.
Change-Id: I7f3dbfa965b9dcbade8b2f06a5bd2ac1345c7972
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This reverts commit 2fdfa50437.
Reason for revert: libbl31.a is under refactoring. Stop linking to this
library before finalizing the binary. This patch will be re-landed when
the binary is ready.
BUG=b:412560091
Change-Id: Ie2c315141a51f30027414cfe59552cb50f2b52f6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87414
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use GPP_C08 as the GPIO_PCH_WP.
BUG=b:409472563
Test=TEST=wp status update verified by toggling it on and off.
Change-Id: I0f6c7c051b2d38a787fe3bb21266a6ef6ebc487b
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87413
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Two ME current working state definitions are missing. They are
needed for CB:85413. Get them from intelmetool.
Change-Id: Ie163c4b29155e3fd44f0cb3096f825c84da37559
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87394
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- some formatting fixes;
- add information about proprietary blobs;
- update information about the tested hardware and operating systems.
Change-Id: I85a8f1df2ffc6e0e1674c4b82888a3964aa8d672
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The memory dump was done for the 1.80 (2023-04-07) version of the
vendor's UEFI.
Change-Id: I649e2c3ae715651b5f0eadc9b52e61e4deae77a1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
It's an ACPI spec violation for a device to have both an _ADR and
a _HID method, so prefer the latter if a HID value is specified
via the chip registers.
Change-Id: I5d84dbea52595e61df56a5ff779d5e0ee0d84bdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87248
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On SoCs like Glinda, CPU cores may exhibit slight variations in
maximum boost frequency, and the L3 cache can be composed of
multiple blocks with different sizes and unique IDs.
Add helper functions,
1. get_max_boost_frequency() to compute max boost frequenncy.
2. ap_stash_core_info() to update core_info struct with max boost
frequency & all L3 cache block uniq ID & its size.
To accurately determine the total L3 cache size:
1. Retrieve L3 cache information for each CPU core.
2. Identify the unique cache ID associated with each core.
3. Aggregate cache sizes for all unique cache IDs to compute the
total L3 cache size, ensuring correct summation when L3 cache
blocks have different sizes.
TEST=Build for Glinda SoC, with L3 cache = 16MB + 8MB. Ran command
'dmidecode -t 7' & verified L3 cache is 24MB(Previously it was
wrongly reported as 32MB).
Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85640
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the interrupts coming from the sensors into the ISH.
BUG=b:410645679
Change-Id: I2acaed1900e248cfe7fcc81201c6991a9741f26c
Signed-off-by: Yuval Peress <peress@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87333
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
