Provide staged GPIO pad configuration for the M.2 NVMe SSD and the
(discrete) M.2 2230 wireless module on supported StarBook variants.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6b3b607e73a2b1c437349f31cc6faaf662365da7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Implement Fatcat-style 3-stage M.2 NVMe slot sequencing
(PWREN, PERST#, CLKREQ#) for StarFighter and apply it to
all NVMe-capable ports (both Gen3 and Gen4).
This addresses intermittent NVMe detection problems on
cold/warm boot and improves PCIe link speed negotiation
by ensuring the device is held in reset with clocks gated
until slot power is enabled and coreboot is about to
initialize devices.
Sequence per NVMe port:
1) pre-mem: disable CLKREQ#, assert PERST#, PWREN=0
2) BS_PRE_DEVICE exit: PWREN=1, enable CLKREQ# native,
keep PERST# asserted
3) BS_DEV_INIT_CHIPS entry: deassert PERST#
Also update the variant gpio_table defaults so PWREN stays
off and CLKREQ# stays disconnected until the sequencing
code enables them.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic34e9e755e167e301348fbe7c75649401300f53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90974
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a shared helper (behind Kconfig) that owns the ramstage bootstate
ordering for the Star Labs NVMe/M.2 slot power sequence (PWREN, PERST#,
CLKREQ#).
Boards/variants provide pad configs for stage 2 and stage 3 either by
implementing the `variant_nvme_power_sequence_*()` helpers or by
providing pad tables via `variant_nvme_power_sequence_pads()` and
`variant_nvme_power_sequence_post_pads()`.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3d518c35c26f3d3ee1dd72b4a35861d19cdb85ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90973
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove CMOS option tables and defaults from Star Labs boards now that
EC state is persisted through EFI variable store options.
Drop remaining Merlin EC CMOS plumbing (RTC reads and ACPI fields) and
read settings only via the option backend.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cc7f6240adc4b396912d566c7de176d4d2cb92b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
When STARLABS_ACPI_EFI_OPTION_SMI is enabled, store and restore
trackpad and keyboard backlight state across S4/S5 using the EFI
variable store SMI bridge instead of CMOS.
Also make the EC init paths treat CMOS as an index mapping and
prefer the option backend when CMOS options are not in use.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia31ac0440eba1334be48030ce7fe03dc84193ac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91304
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a Device NVS (DNVS) protocol and SMM handler to let ACPI read and
write a restricted set of coreboot options stored in the UEFI variable
store.
ACPI fills DNVS and triggers an SMI via APM_CNT (0xB2). SMM performs
the requested operation and updates DNVS with status and, for reads,
the returned value.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ice0ac36f6d0e1de88daf7010cb1771453547619e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91303
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extend get_microcode_info() to return the microcode size.
This is being used in the following commit which uses the size
to copy the microcode update to RAM in order to speed up MPinit.
Depending on the SPI flash interface speed, the microcode size and
the number of APs this can improve boot time by seconds.
Since microcode size isn't used yet this is not a functional change.
Change-Id: I1385e04c56e1411f0847a1c201c17e460c957477
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90894
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move loading of microcode to pre_mp_init() as found on other
Intel CPU drivers. There’s no need to cache the microcode location
since intel_microcode_find() already caches it.
No function change, thus untested.
Change-Id: I05bbb074d189594027916c6a3b04270bd3b6edd1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90892
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Because GPP_B05 is not required for EC or ISH interrupts,
it should be set to NC in coreboot to minimize power impact.
BUG=b:475879711
TEST=Build and boot to OS.
Change-Id: Ic56e16ca89968c8e2204d1609812f1d8d3548512
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The charging debug access port was previously only configured during
slow battery charging. Move this configuration into a dedicated
function, configure_charging_debug_access(), and call it within the
common mainboard_init() path.
This ensures the debug access port is consistently configured during
mainboard initialization, following the same pattern as parallel
charging.
BUG=b:488143407
TEST=Build Bluey/Quartz
Change-Id: Idacffd61834e0700619b240dfe362f3be90badb9
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91505
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add a common low battery poweroff implementation in
soc/mediatek/common/low_battery.c. This implementation checks
if a low battery shutdown is needed and triggers a poweroff
via Chrome EC if necessary.
Also enable this for mt8196 in ramstage.
BUG=b:424707341
TEST=The FW draws low battery indicator and powers off the DUT after 5
seconds.
TEST=Use `elogtool list` and see `Low Battery boot | Power Off`
Change-Id: I2fcd242fbf26bdebc4acfb477c95c381adf645f5
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91431
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
The current VBUS enablement logic was found to be unnecessary for
USB host functionality on x1p42100. Forcing VBUS power via the PMIC's
OTG buck is not required for the current hardware configuration and
could lead to incorrect power state management.
Remove the enable_vbus_ss() function and associated SCHG DCDC
register definitions from the SoC driver. This streamlines the
USB initialization path to focus solely on PHY and controller
setup.
TEST=Verify USB detection in the depthcharge on Google/Quartz.
Change-Id: Ie30878802831419f3d70ea921f7f46a262db99bb
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Set the SCHG_DCDC_OTG_CFG register to 0x26 during USB initialization
to ensure the OTG buck is correctly configured for host mode.
TEST=Verify USB detection in the depthcharge on Google/Quartz.
Change-Id: If76be8b7210fc86f473bfd77eb56718f28f19eae
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Currently, mainboards that do not support Google TPM must manually
define stubs for chromeos_device_branded_plus_hard() and
chromeos_device_branded_plus_soft() to satisfy the linker.
Move these stubs into vendorcode/google/chromeos/chromeos.h as static
inline functions when CONFIG(TPM_GOOGLE) is disabled. This reduces
code duplication and allows the removal of redundant stub definitions
in the ptlrvp mainboard.
Change-Id: If270d4815c687a409fec7058c224f987f9e2741a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91474
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce EC_GOOGLE_CHROMEEC_LED_CONTROL to allow boards to opt-in to
manual LED/lightbar synchronization. This ensures that the AP firmware
can coordinate the lightbar state with boot animations or specific
power states (like critical battery alerts) without forcing the logic
on all ChromeEC-based platforms.
On Bluey, the lightbar logic is refactored into a helper function
`platform_init_lightbar()` to improve readability and is now gated
by the new Kconfig. Similar gating is applied to Fatcat's romstage.
Summary of changes:
- Add EC_GOOGLE_CHROMEEC_LED_CONTROL Kconfig option.
- Bluey: Refactor lightbar init into a helper and gate by Kconfig.
- Fatcat: Gate early lightbar initialization by Kconfig.
Change-Id: I6b0294b73b8b9929a6be0e15bf64f7e688b7da8c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add launch_charger_applet() to handle the system state when booting
in off-mode charging or low-power modes with a charger present.
Key features:
1. Monitoring: Periodically checks battery current (I-current) via
SPMI/PMIC registers.
2. Event Handling: Detects and clears EC power button and lid events.
If a manual power-on event is detected, the system triggers a
full board reset to ensure a clean boot to the OS (preventing
firmware state conflicts like ADSP-lite vs ADSP).
3. Shutdown: If the charger is removed, it signals the EC via
off-mode heartbeat and initiates an AP power-off.
BUG=b:439819922
BRANCH=None
TEST=Verified that the device enters the charging loop when plugged
in while off, and transitions to a full boot when the power button
is pressed.
Change-Id: I152f71eac89f5b522ea7b286517724e213c31e9a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91485
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement google_chromeec_offmode_heartbeat() to wrap the
EC_CMD_ENABLE_OFFMODE_HEARTBEAT host command.
This allows the AP to signal the EC to maintain the power state
required for off-mode UI (such as the charging applet) during
shutdown or low-power transitions.
BUG=b:439819922
BRANCH=none
TEST=Build and verify that the charger applet can successfully
call this function to enable heartbeat signaling.
Change-Id: Ic2ed464bf454e614a098ee5bbbb662adc9d79144
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91484
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Add the SoC hook to initialize SPI TPM decoding. Without the additional
programming an attempt to talk to SPI TPM hangs the platform when the
TPM_MEASURED_BOOT_INIT_BOOTBLOCK is set. If TPM is initialized in
ramstage, the OpenSIL programs the SPI TPM decoding properly and the
issue is not observed.
TEST=Select TPM_MEASURED_BOOT_INIT_BOOTBLOCK and enable
TPM_MEASURED_BOOT on Gigabyte MZ33-AR1, and observe the platform does
not hang in bootblock.
Change-Id: I2e6c0aad31fd0335e0d16111ed4894a12d2ba497
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Rename the PL4 powercap Kconfig symbol to MB_STARLABS_PL4_WATTS
and update the common powercap logic to use the namespaced
option.
Change-Id: If36d087accc13a03eac4715948a4ca47bd70c3c4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91461
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the BOARD_STARLABS_LITE_ADL preprocessor hook with a
weak baseboard function and provide the StarLite-specific SSDT
generator from the i5 variant directory.
Change-Id: Iea1a27fe1bf86bf970bd7021135760d8a1bc75a1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91460
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All Star Labs ADL boards select SOC_INTEL_COMMON_BLOCK_ASPM, so the
additional preprocessor guard in the PCIe CFR form is redundant.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id7cd4911666c02f88a9c1c5f074ac996744be23d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91459
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the i5 variant-specific CFR callbacks out of the baseboard
CFR menu and compile them from the variant directory. This
reduces preprocessor usage in the common file.
Change-Id: Ic03ec18aed100a95d347c49c2b1deecf1c3fd961
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Move StarLite Mk V (Lite ADL) into the ADL grouping under
src/mainboard/starlabs/adl/.
Like StarBook Horizon, keep common code in the ADL directory and place
model-specific data under src/mainboard/starlabs/adl/variants/ using the
SKU-style variant directory (i5).
Update MAINBOARD_DIR and related paths so binary blobs, SPD data and
CMOS layout continue to resolve correctly, and update documentation to
reflect the new blobs path.
Note that BUILD_TIMELESS ROM hashes change since MAINBOARD_DIR is
embedded in the CBFS config file.
BUG=None
TEST=BUILD_TIMELESS=1 build STARLABS_LITE_ADL
Change-Id: Ib367bc65ad63e848d9e20e7d55f542f135b3c1d5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91256
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the Star Labs Byte (Mk II / Mk III) into the ADL grouping under
src/mainboard/starlabs/adl/.
Like StarBook Horizon, model differences live under
src/mainboard/starlabs/adl/variants/ using SKU-style variant directories
to share common configuration. Byte Mk II (ADL) and Byte Mk III (TWL)
share a single "y2" variant directory.
Update MAINBOARD_DIR and CMOS layout handling so binary blob paths and
NVRAM options continue to resolve correctly.
Update the documentation to reflect the new blobs path.
Note that BUILD_TIMELESS ROM hashes change since MAINBOARD_DIR is
embedded in the CBFS config file.
BUG=None
TEST=BUILD_TIMELESS=1 build STARLABS_BYTE_ADL
Change-Id: I4b6be115a4ab2316d5ca4cc8e656e3643518273e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91255
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the card reader USB port, along with ACPI driver info
and the CFR option to control it.
Change-Id: I30dd26438f0a7b355061a45b9ffb7f447c89a751
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set the default power profile to Performance, regardless of whether
there is a fan present.
Change-Id: Id1d624355f9f08b5abb154e26026e70675322ddb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As the card reader isn't on a dedicated USB interface for all variants
for the StarLite, default to disable to ensure that an unused USB port
isn't enabled.
Change-Id: I2176fd6556797e468012c98f7e482b9573b5e3f7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Move the SOC_I2C_DEVFN(n) macro definitions that were duplicated in a
separate "for common code" section at the end of multiple platform
pci_devs.h files.
Platforms affected:
- Alder Lake
- Cannon Lake
- Elkhart Lake
- Jasper Lake
- Skylake
- Tiger Lake
Change-Id: Ie3b3e6a25b0dba1beeadad1ab9acf59cafdbcf4a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Migrate Tiger Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.
This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/tigerlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation
Tiger Lake uses PCH_DEV_PMC as the PMC device identifier.
Change-Id: Ibe06e4d100b2715aeccfe0ff85dc944ab6cd80fc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91297
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Panther Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.
This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/pantherlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation
Panther Lake uses PCI_DEV_PMC as the PMC device identifier.
TEST=Build and boot to the OS on a Fatcat device
Change-Id: I32bf4b678e7edda598319086acccc4983edcbe3e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91296
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Meteor Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.
This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/meteorlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation
Meteor Lake uses PCI_DEV_PMC as the PMC device identifier.
Change-Id: Ia21a6ee0c6fbee6d4ffcfce5fdbe9b3bdf5fcece
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91295
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Alder Lake to use the common PCH client SMI handler
implementation from the Intel common feature code. This change
eliminates platform-specific code by leveraging the shared smihandler.c
driver.
This commit:
- Adds SOC_PMC_DEV macro definition to soc/pci_devs.h
- Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig
- Removes src/soc/intel/alderlake/smihandler.c
- Updates Makefile to remove smihandler.c compilation
Alder Lake uses PCH_DEV_PMC as the PMC device identifier.
Change-Id: Icbbc7af25e73e952c9b5f811cf0bbe01efe3ae94
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Add a common implementation of SMI handler code for PCH client platforms
to reduce code duplication across Alder Lake, Meteor Lake, Panther Lake,
and Tiger Lake platforms.
This implementation consolidates:
- smihandler_soc_disable_busmaster(): Skip disabling PMC bus master
- southbridge_smi array: Standard SMI handler mappings
The common driver uses a platform-specific macro that must be defined in
each platform's soc/pci_devs.h header:
- SOC_PMC_DEV: PMC PCI device identifier
This change enables consolidation of nearly identical smihandler.c files
across four platforms, reducing duplication by approximately 100+ lines.
Change-Id: I9ecb65b7ea4feafb8acbaf5798bbeaeb80b7c24a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91293
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Meteor Lake to use the common PMC utility driver instead
of maintaining platform-specific pmutil.c code.
This change:
- Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig
- Removes platform-specific pmutil.c
- Removes pmutil.c from Makefile.mk
The common driver provides all necessary functionality through
the generic config_t interface, eliminating ~290 lines of
duplicated code.
Change-Id: I1c46a517420c8ea7410c4ed7e8e7b761d4399cf9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Migrate Panther Lake to use the common PMC utility driver instead
of maintaining platform-specific pmutil.c code.
This change:
- Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig
- Removes platform-specific pmutil.c
- Removes pmutil.c from Makefile.mk
The common driver provides all necessary functionality through
the generic config_t interface, eliminating ~290 lines of
duplicated code.
TEST=Build and boot to the OS on a Fatcat device
Change-Id: I3ee9630a6b15d7b02776ff633a3cff0766a8915b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91239
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Alder Lake to use the common PMC utility driver instead
of maintaining platform-specific pmutil.c code.
This change:
- Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig
- Removes platform-specific pmutil.c
- Removes pmutil.c from Makefile.mk
The common driver provides all necessary functionality through
the generic config_t interface, eliminating ~290 lines of
duplicated code.
Change-Id: Ieb62ffac95550a0ae8607a3a9ae76e0f6ff0ac35
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
This adds a common PM utility driver for modern Intel platforms that
share consistent PM register layouts.
The driver consolidates power management utility functions that were
previously duplicated across multiple Intel SoC platforms. This
includes functions for:
- SMI/TCO/GPE status bit decoding
- PMC MMIO base address access
- RTC failure detection
- Sleep state management
- Power state structure population
- After-G3 power state configuration
- GPE configuration retrieval using generic config_t
The GPE configuration function (soc_get_gpi_gpe_configs) uses the
generic config_t typedef that each platform defines, allowing complete
code reuse without platform-specific shims.
This common driver is controlled by the Kconfig option
SOC_INTEL_COMMON_FEATURE_PMUTIL and is built for all boot stages.
Change-Id: I45b829b7c18ee66474457df5523069f930806b35
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/elkhartlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
Change-Id: I59d9cb1b37bca2c682e2bf87fc3f5b24c34fb920
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/jasperlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
Change-Id: Ied29a5f2dabdebe0afedd1d69e4a817d6606a82d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/tigerlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
Change-Id: I65f8af8f5abccff25ec0dead4f7def7ce16d3081
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91220
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/pantherlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
TEST=Build and boot to the OS on a Fatcat device
Change-Id: If5f2de9faa209ff30f986f34b1816ffa6d5fc683
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91219
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/meteorlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
Change-Id: Ifb198964c5eda1fceaec6111cd7fba374bacf1b6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific espi.c with the common eSPI/LPC
initialization driver.
Changes:
- Remove src/soc/intel/alderlake/espi.c
- Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig
- Update Makefile.mk to remove espi.c from build
The eSPI/LPC initialization was nearly identical across platforms,
differing only in minor header inclusions and ENV_RAMSTAGE wrapper
usage. The common implementation uses the config_t typedef that
each platform defines, providing clean abstraction without
preprocessor conditionals.
Change-Id: Ifacdd480a9cfd59d9e54faebad82e1cc2db8a8ed
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91217
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This introduces a common implementation for eSPI/LPC initialization
that handles generic IO decode range configuration and standard
interrupt setup. This code is nearly identical across multiple Intel
client platforms.
The implementation includes:
- soc_get_gen_io_dec_range(): Configures generic IO decode ranges
from devicetree (gen1_dec through gen4_dec)
- lpc_soc_init(): Performs legacy ISA/DMA initialization, enables
CLKRUN for power gating, configures Serial IRQ mode, and sets up
the interrupt controllers (IOAPIC, PIRQ, i8259)
Platform-specific configuration is handled through the config_t
typedef that each platform defines via its soc_chip.h header,
eliminating the need for preprocessor conditionals.
The common driver is enabled via the SOC_INTEL_COMMON_FEATURE_ESPI
Kconfig option and works across bootblock, romstage, and ramstage.
Platforms that will use this common implementation:
- Alder Lake
- Meteor Lake
- Panther Lake
- Tiger Lake
- Jasper Lake
- Elkhart Lake
Change-Id: Idbdecff1cef44dae90afb35ff6e2afca011ea5b4
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91216
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Tiger Lake to use the common SoundWire driver implementation
from the Intel common feature code. This change eliminates platform-
specific code by leveraging the shared soundwire.c driver.
This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig
- Removes src/soc/intel/tigerlake/soundwire.c
- Updates Makefile to remove soundwire.c compilation
Tiger Lake uses the default values (4 SoundWire master links with ACPI
address 0x40000000).
Change-Id: Ife743d28c8760d9de3f593f7d8caafd7a73efe3a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
