Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as vell is using a converged firmware image.
This effort also helps to save vell boot time by 80-100ms as RPL FSP is
better optimized.
Additionally, Raptor Lake platform only needs 1 SIPI-SIPI which saves
10ms of the boot time.
BUG=b:352330495
TEST=Able to build and boot google/vell.
warm reboot time w/o this CL
```
Total Time: 1,408,669
```
warm reboot time w/ this CL
```
Total Time: 1,235,651
```
Change-Id: I8f7dd76f00cfeff2908aeb805524706ac23403fa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84491
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables unused I2C6 controller for the 'vell' variant of
the 'brya' mainboard.
BUG=b:352330495
TEST=Able to build and boot google/vell.
Change-Id: I5b39e44bb64bf2285c962249c0d94a8d5325f0c7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Create the kanix variant of the rex0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:368501705
TEST=util/abuild/abuild -p none -t google/rex -x -a
make sure the build includes GOOGLE_KANIX
Change-Id: Id74a084ed3cebb65625166e3098f43e41a63f5f9
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84432
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Earlier change (https://review.coreboot.org/c/coreboot/+/84019)
pushed to resolve the privacy LED blinking issue regressed the camera
autofocus functionality. This change updates the power resource for
NVM and VCM in line with the tivviks schematics to fix the issue.
BUG=b:365899407
TEST=Build and boot tivviks. Verified the Autofocus and all the
camera basic sanity tests.
Change-Id: Id3e256d59982ac176844e289f18ee450079704b9
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Compared to MT8186, MT8186T requires initializing the PMIC MT6319 in the DTS file, which necessitates using different SKU ID to distinguish between the MT8186 and MT8186T.
For MT8186, factory pre-flashed 0x7fffffff as unprovisioned SKU ID and
kernel can use the corresponding DTS file. To make MT8186T functional
on unprovisioned devices, change the SKU ID to 0x7ffffeff, so that the
correct DTS file will be selected by the payload.
BUG=b:365730137
TEST=1. Pre-flashed 0x7fffffff and boot OS.
2. Check OS boot normally by 0x7ffffeff.
BRANCH=corsola
Change-Id: I91306d3abd508e104851916882fb36a4fd302036
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84342
Reviewed-by: Knox Chiou <knoxchiou@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I6012fd948b4350bda7af5390badac737553fa872
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84430
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Similarly to what is done in Meteor Lake, the PortResetMessageEnable
UPD can be set based on usb2_port[].type_c setting and therefore
usb2_port_reset_msg_en is not necessary.
BUG=b/348678529
TEST=Build for fatcat
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d57
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84429
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Each TCSS port can be associated a setting via the tcss_cap_policy
device tree field. The setting can be picked within five values listed
by this commit.
BUG=b/348678529
TEST=fatcat board build tcss_cap_policy[0]=TCSS_TYPE_C_PORT_FULL_FUN
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d56
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Because PLATFORM_USES_FSP2_X86_32 default to false when
PLATFORM_USES_FSP1_1, efi_datatype.h wrongly defines EFI as
__attribute__((__ms_abi__)).
TEST=When some code involved in the build of a platform using
FSP 1.1 such as Google/CYAN includes efi_datatype.h, it does
not hit the following error: '__ms_abi__' calling convention
is not supported for this target
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84402
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I08881e3fb25abca8c34a04b3bea6534c0dbf391a
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84424
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mediatek SoCs start operating at eMMC clock around 3MHz right after
power-on due to wrong src_hz value. In JEDEC spec, eMMC clock needs
under 400kHz.
When we need to set a clock output frequency, we actually set a
frequency division value. Originally, we set the source clock
frequency to 50MHz, the target frequency to 400KHz, and get the
division value 128. However, the actual source clock frequency is
400MHz, so the final actual output is 400MHz/128=3.125MHz.
So we correct source clock frequency to 400MHz for eMMC output
clock of 400KHz.
BUG=b:356578805
TEST=test boot ok; measure eMMC clock ok; no boot time impact
Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84298
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to add GPE1 block
rather than checking if GPE1_STS(0) is '0'.
BUG:362310295
TEST=with the flag, boot google/fatcat or intel/ptlrvp to OS and check
that FADT table includes GPE1. FADT should have:
GPE1 Block Address : 00001810
GPE1 Block Length : 18
GPE1 Base Offset : 80
Without the flag, boot to OS and check that FADT table does not include
GPE1. FADT should have:
GPE1 Block Address : 0
GPE1 Block Length : 0
GPE1 Base Offset : 0
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Due to beadrix DB has C1 port before, and add FW_CONFIG without C1 port for LTE sku.
BUG=b:364431483
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
Set fw config to DB_PORTS_LTE and check
1.fw_config match found: DB_PORTS=DB_PORTS_LTE <= show LTE present message
2.USB3 port 3: enabled 1 <= LTE port enable
Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69
Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84232
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
psys is not an optimal solution for no/low battery boot. Hence remove
function and macros related to psys implementation.
BUG=b:335046538
BRANCH=None
TEST=Build and boot on brox board
Change-Id: I6c0e9561367b5846b00be27012f002dd7c299414
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84397
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I01db9dad872cd4c9238b6c6aac73f3e6367710a4
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I3870bcd2482e55a5abcbd27cd0be18f25a35afbc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84415
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.
Change-Id: Ied08e5e9fe4913bd60474ed7dcf88b945172558d
Signed-off-by: Jeremy Soller <jeremy@sysetm76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In newer SOC, such as PTL, there is no DMI. Exclude DMI memory range in
northbridge.asl if DMI_BASE_SIZE is '0'
BUG=b:348678529
TEST=Build CB with DMI_BASE_SIZE set to '0' in the SOC directory. Boot
to OS and check ACPI PDRC device from the ACPI DSDT table. There should
not have an entry for DMI in its _CRS method.
Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84349
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If real-time tuning was enabled, 'PchPwrOptEnable' was set two times
with different values. This patch fixes the issue.
BUG=none
TEST=Enabled FSP UPD debug output and checked 'PchPwrOptEnable' offset
Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84399
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The real-time feature should also be activated for all mc_ehl
mainboards, as it has already been done for mainboard mc_ehl1. It
improves performance in the real-time environment for these mainboards.
Change-Id: I04859b2f32bc11344b0620925f2414e7a6df625e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84391
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ordering of the USB-C port locations is swapped. When facing the
left panel, the correct ordering is port 1 (left) then port 0 (right).
Swap the positions of the two USB-C ports to their correct values.
BUG=b:349822718
TEST=Booted to OS, confirmed correct physical_location at
/sys/class/typec.
Change-Id: I98e3042c64aba885b602c99916734c2dbb9d66bd
Signed-off-by: Jameson Thies <jthies@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84403
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ELOG for CSE updates was being added in fsp_params.c, but the
actual update happens in cse_lite.c. This commit moves the ELOG to
cse_lite.c to more accurately reflect where the event is happening.
This also removes the need for a sol_type variable in
meteorlake/romstage/fsp_params.c.
It also helps to avoid redundant ELOG event entry while performing
CSE update (due to CSE RO to RW switch dependency).
BUG=b:361253028 (Multiple CSE sync elog prints for Nissa/Trulo)
TEST=Able to see only one instance of ELOG while performimg CSE sync.
w/o this patch:
elogtool list
0 | Log area cleared | 4088
1 | Kernel Event | Clean Shutdown
2 | Early Sign of Life | MRC Early SOL Screen Shown
3 | Early Sign of Life | CSE Sync Early SOL Screen Shown
4 | System boot | 29
5 | Memory Cache Update | Normal | Success
6 | Early Sign of Life | CSE Sync Early SOL Screen Shown
w/ this patch:
elogtool list
0 | Log area cleared | 4088
1 | Early Sign of Life | MRC Early SOL Screen Shown
2 | Memory Cache Update | Normal | Success
3 | System boot | 30
4 | Memory Cache Update | Normal | Success
5 | Early Sign of Life | CSE Sync Early SOL Screen Shown
Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I60bb9e7df368b786e17bb49a6f35d27372fd21de
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84394
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I5cf34d8c4e27835d126eb66f2015d2e9d93b700f
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake-up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
4. PTL replaces DMI3 with SAF to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE guard check is added in northbridge.asl
5. include GPIO ASL that supports new pinctrl schema.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit drops redundant CRASHLOG option for the brox and brya
mainboards as SOC_INTEL_CRASHLOG config is now selected by the
Alder Lake SoC directly.
TEST=Able to build and boot google/brox w/o any functional impact of
the crashlog feature.
Change-Id: I83859d6e61a151d6930785df3466c185c69e8e66
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84366
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the CRASHLOG config option for Chrome OS boards. This allows the
Chrome OS crash reporter to collect and analyze crash dumps, aiding in
debugging and improving system stability.
TEST=Able to build and boot google/brox
Change-Id: Ia23ef1cbebdba9a3b724204eb25ee788afa3e8fd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch configures the GPIO pins for ISH to notify EC about the
tablet mode change in accordance with schematic_20240607.
BUG=b:347811875
TEST=Build and boot google/trulo. Placed the device in tabletmode & on
EC console,"tabletmode" command shows "tablet mode".
Change-Id: Id22e397e46b522428ffdabe34a445ed7e4fb6fc5
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This reverts commit 88a496a9c8.
This workaround is not valid with the latest Intel PRQ silicon,
so I'm dropping it now. Additionally, able to boot to ChromeOS without
any hang, and I also ran an S0ix cycle without any failures.
BUG=b:244082753
TEST=Able to boot google/rex0 to CrOS.
Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84368
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes the redundant crashlog config (SOC_INTEL_CRASHLOG)
entry from BOARD_GOOGLE_BRYA0 and BOARD_GOOGLE_BRASK.
BOARD_GOOGLE_BRYA_COMMON already selects a crashlog config, and
brya0/brask board eventually selects the BOARD_GOOGLE_BRYA_COMMON
config, making SOC_INTEL_CRASHLOG redundant.
TEST=Successfully built and booted google/brya0.
Change-Id: Iaff7954d4dafb4c6ca72a1521dfb434fb36b495a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84364
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes the redundant crashlog config (SOC_INTEL_CRASHLOG)
entry from BOARD_GOOGLE_BASEBOARD_BROX. BOARD_GOOGLE_BROX_COMMON
already selects a crashlog config, and brox baseboard eventually selects
the BOARD_GOOGLE_BROX_COMMON config, making SOC_INTEL_CRASHLOG
redundant.
TEST=Successfully built and booted google/brox.
Change-Id: Idcb03d13ee3943f188246663d47f47cb8afccbd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84363
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Commit bc8f5405b5 ("tgl mainboards: Move usb{2,3}_ports settings into
XHCI device scope") not only moved the USB port definitions under the
XHCI device reference, but also combined multiple register definitions.
In doing so, it broke the inheritance from the baseboard, since the
variant overridetree registers now replaced the entire usb2_ports/
usb3_ports structs, rather than replacing individual array elements
therein. This resulted in any USB ports inherited from the baseboard
and not overridden by the variant being non-functional as they were
not included in the resulting combined devicetree.
To fix this, return to overriding individual array elements in the
usb2/3_ports structs.
TEST=build/boot google/drobit. Verify all USB ports present and
functional. Verify mainboard/static.c in built shows all ports.
Change-Id: I54921fa4ecf594a1ecbcfa7c45e5d745d4a95652
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84348
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
1)Modify jubilant cpu power limit setting depend on the brox
baseboad settgins,refer to CL:
https://review.coreboot.org/c/coreboot/+/83752
2)Update PL1,PL2, and PL4 value from jubilant thermal design
PL1 = 15W
PL2 = 41W
PL4 = 87W
BUG=b:364441688
BRANCH=None
TEST=Able to successfully boot on jubilant photo SKU1 and SKU2
boards with AC w/o battery.
Test on AC 65W and 45W w/o battery,and check the PL values.
Change-Id: I9a143d9faaa6c57b0d314c0ff6c0e55f556d7216
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
This commit refactors the long battery string implementation to include
caching of the EC response for battery information (model, serial, and
manufacturer).
This optimization reduces resume time by approximately 63ms by
minimizing communication overhead between the AP and EC.
BUG=b:366338622
TEST=Verified on google/tivviks_ufs:
* Long battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled.
* Short battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n.
Change-Id: I32ae5b5e618f20335f3d344811a97f1416df529e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Older ChromeOS devices (pre-CR50) do not support reading long battery
strings. This commit adds a Kconfig option,
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING, to enable or disable this
feature.
This allows devices with TPM_GOOGLE (CR50/TI50) to read and display
long battery strings, while older devices like google/link, wolf, samus,
and chell will continue to display only the first 8 characters.
This change ensures compatibility with older devices while enabling
the display of complete battery information on newer platforms.
BUG=b:366338622
TEST=Verified on google/tivviks_ufs:
* Long battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled.
* Short battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n.
Change-Id: I7859809278b7e926bbe8beb1a0a9e12c7e6c220d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84352
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
FSP n-1 headers in vc/intel/fsp/fsp2_0/graniterapid are updated to
pass compilation with full platform codes.
Change-Id: I1d13ddd4db8409a4928bd1bf152a9c284d138e48
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
For Xeon-SP, DCACHE_BSP_STACK_SIZE is by default 0x10000. For GNR,
this default size is enough. Use the default size so that more
CAR spaces could be saved for other purpose.
Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84302
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
