mainboard/google/{brox,brya}: Drop redundant CRASHLOG config
This commit drops redundant CRASHLOG option for the brox and brya mainboards as SOC_INTEL_CRASHLOG config is now selected by the Alder Lake SoC directly. TEST=Able to build and boot google/brox w/o any functional impact of the crashlog feature. Change-Id: I83859d6e61a151d6930785df3466c185c69e8e66 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84366 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
e26d8d064d
commit
c512585e55
2 changed files with 0 additions and 2 deletions
|
|
@ -37,7 +37,6 @@ config BOARD_GOOGLE_BROX_COMMON
|
|||
select SOC_INTEL_COMMON_BLOCK_TCSS
|
||||
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
|
||||
select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE
|
||||
select SOC_INTEL_CRASHLOG
|
||||
select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1
|
||||
|
||||
config BOARD_GOOGLE_BASEBOARD_BROX
|
||||
|
|
|
|||
|
|
@ -44,7 +44,6 @@ config BOARD_GOOGLE_BRYA_COMMON
|
|||
select SOC_INTEL_CSE_SEND_EOP_ASYNC
|
||||
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P
|
||||
select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE
|
||||
select SOC_INTEL_CRASHLOG
|
||||
select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1
|
||||
select SOC_INTEL_STORE_ISH_FW_VERSION if DRIVERS_INTEL_ISH
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue