erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZE

Browse source 
For Xeon-SP, DCACHE_BSP_STACK_SIZE is by default 0x10000. For GNR,
this default size is enough. Use the default size so that more
CAR spaces could be saved for other purpose.

Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84302
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Gang Chen 2024-07-11 06:51:43 +08:00 • committed by Lean Sheng Tan
commit 2f56049778
1 changed files with 0 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

9
src/soc/intel/xeon_sp/gnr/Kconfig
View file

@ -56,15 +56,6 @@ config DCACHE_RAM_SIZE
and/or romstage. FSP-T reserves the upper 0x100 for
FspReservedBuffer.
config DCACHE_BSP_STACK_SIZE
hex
default 0x60000
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. It needs to include FSP-M stack requirement and
CB romstage stack requirement. The integration documentation
says this needs to be 256KiB.
config FSP_M_RC_HEAP_SIZE
hex
default 0x142000