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soc/intel/ehl/fsp_params: Do not re-enable 'PchPwrOptEnable' for real-time tuning

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If real-time tuning was enabled, 'PchPwrOptEnable' was set two times
with different values. This patch fixes the issue.

BUG=none
TEST=Enabled FSP UPD debug output and checked 'PchPwrOptEnable' offset

Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84399
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer 2024-09-17 15:06:50 +02:00 • committed by Werner Zeh
commit 9c51ca52a4
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/elkhartlake/fsp_params.c
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@ -333,6 +333,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->D3ColdEnable = 0;
params->PmcOsIdleEnable = 0;
} else {
params->PchPwrOptEnable = 1; /* Enable PCH DMI Power Optimizer */
params->PchPostMasterClockGating = 1;
params->PchPostMasterPowerGating = 1;
}
@ -471,7 +472,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Custom1TurboActivationRatio = 0;
params->Custom2TurboActivationRatio = 0;
params->Custom3TurboActivationRatio = 0;
params->PchPwrOptEnable = 0x1; //Enable PCH DMI Power Optimizer
params->TStates = 0x0; //Disable T state
params->PkgCStateLimit = 0x7; //Set C state limit to C9
params->FastPkgCRampDisable[0] = 0x1;