soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake-up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
4. PTL replaces DMI3 with SAF to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE guard check is added in northbridge.asl
5. include GPIO ASL that supports new pinctrl schema.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Ravi Sarawadi
Subrata Banik
parent
c512585e55
commit
c43b19ff38
12 changed files with 2932 additions and 0 deletions
|
|
@ -14,6 +14,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
|
|||
select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS
|
||||
select DEFAULT_X2APIC_LATE_WORKAROUND
|
||||
select DISPLAY_FSP_VERSION_INFO_2
|
||||
select DRIVERS_USB_ACPI
|
||||
select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
|
||||
select FSP_COMPRESS_FSP_S_LZ4
|
||||
select FSP_M_XIP
|
||||
|
|
@ -50,6 +51,13 @@ config SOC_INTEL_PANTHERLAKE_BASE
|
|||
select SOC_INTEL_COMMON_BASECODE
|
||||
select SOC_INTEL_COMMON_BASECODE_RAMTOP
|
||||
select SOC_INTEL_COMMON_BLOCK
|
||||
select SOC_INTEL_COMMON_BLOCK_ACPI
|
||||
select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
|
||||
select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
|
||||
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
|
||||
select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
|
||||
select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
|
||||
select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
|
||||
select SOC_INTEL_COMMON_BLOCK_CAR
|
||||
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
|
||||
select SOC_INTEL_COMMON_BLOCK_CNVI
|
||||
|
|
|
|||
51
src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
Normal file
51
src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#define R_ICLK_PCR_CAMERA1 0x8000
|
||||
#define B_ICLK_PCR_FREQUENCY 0x1
|
||||
#define B_ICLK_PCR_REQUEST 0x2
|
||||
|
||||
/* The clock control registers for each IMGCLK are offset by 0xC */
|
||||
#define B_ICLK_PCR_OFFSET 0xC
|
||||
|
||||
Scope (\_SB.PCI0) {
|
||||
|
||||
/* IsCLK PCH base register for clock settings */
|
||||
Name (ICKB, 0)
|
||||
ICKB = PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1
|
||||
/*
|
||||
* Helper function for Read And Or Write
|
||||
* Arg0 : Clock source select
|
||||
* Arg1 : And data
|
||||
* Arg2 : Or data
|
||||
*/
|
||||
Method (RAOW, 3, Serialized)
|
||||
{
|
||||
OperationRegion (ICLK, SystemMemory, (ICKB + (Arg0 * B_ICLK_PCR_OFFSET)), 4)
|
||||
Field (ICLK, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
VAL0, 32
|
||||
}
|
||||
Local0 = VAL0
|
||||
VAL0 = Local0 & Arg1 | Arg2
|
||||
}
|
||||
|
||||
/*
|
||||
* Clock control Method
|
||||
* Arg0: Clock source select (0 .. 5 => IMGCLKOUT_0 .. IMGCLKOUT_5)
|
||||
* Arg1: Frequency select (0: 24MHz, 1: 19.2MHz)
|
||||
*/
|
||||
Method (MCON, 0x2, NotSerialized)
|
||||
{
|
||||
/* Set Clock Frequency */
|
||||
RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1)
|
||||
|
||||
/* Enable Clock */
|
||||
RAOW (Arg0, ~B_ICLK_PCR_REQUEST, B_ICLK_PCR_REQUEST)
|
||||
}
|
||||
|
||||
Method (MCOF, 0x1, NotSerialized)
|
||||
{
|
||||
/* Disable Clock */
|
||||
RAOW (Arg0, ~B_ICLK_PCR_REQUEST, 0)
|
||||
}
|
||||
}
|
||||
923
src/soc/intel/pantherlake/acpi/gpio.asl
Normal file
923
src/soc/intel/pantherlake/acpi/gpio.asl
Normal file
|
|
@ -0,0 +1,923 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/gpio_defs.h>
|
||||
#include <soc/intel/common/acpi/gpio.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/gpio_op.asl>
|
||||
#include <soc/irq.h>
|
||||
#include <soc/pcr_ids.h>
|
||||
|
||||
#define GPIO_SW_REVISION 0x00010000
|
||||
|
||||
/*
|
||||
* Get GPIO DW0 Address
|
||||
* Arg0 - GPIO Number
|
||||
*/
|
||||
Method (GADD, 1, NotSerialized)
|
||||
{
|
||||
/* GPIO Community 0 */
|
||||
If (Arg0 >= COM0_GRP_PAD_START && Arg0 <= COM0_GRP_PAD_END)
|
||||
{
|
||||
Local0 = PID_GPIOCOM0
|
||||
Local1 = Arg0 - COM0_GRP_PAD_START
|
||||
}
|
||||
/* GPIO Community 1 */
|
||||
If (Arg0 >= COM1_GRP_PAD_START && Arg0 <= COM1_GRP_PAD_END)
|
||||
{
|
||||
Local0 = PID_GPIOCOM1
|
||||
Local1 = Arg0 - COM1_GRP_PAD_START
|
||||
}
|
||||
/* GPIO Community 3 */
|
||||
If (Arg0 >= COM3_GRP_PAD_START && Arg0 <= COM3_GRP_PAD_END)
|
||||
{
|
||||
Local0 = PID_GPIOCOM3
|
||||
Local1 = Arg0 - COM3_GRP_PAD_START
|
||||
}
|
||||
/* GPIO Community 4 */
|
||||
If (Arg0 >= COM4_GRP_PAD_START && Arg0 <= COM4_GRP_PAD_END)
|
||||
{
|
||||
Local0 = PID_GPIOCOM4
|
||||
Local1 = Arg0 - COM4_GRP_PAD_START
|
||||
}
|
||||
/* GPIO Community 5*/
|
||||
If (Arg0 >= COM5_GRP_PAD_START && Arg0 <= COM5_GRP_PAD_END)
|
||||
{
|
||||
Local0 = PID_GPIOCOM5
|
||||
Local1 = Arg0 - COM5_GRP_PAD_START
|
||||
}
|
||||
|
||||
Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
|
||||
Return (Local2)
|
||||
}
|
||||
|
||||
/*
|
||||
* Return PCR Port ID of GPIO Communities
|
||||
*
|
||||
* Arg0: GPIO Community (0-5)
|
||||
*/
|
||||
Method (GPID, 1, Serialized)
|
||||
{
|
||||
Switch (ToInteger (Arg0))
|
||||
{
|
||||
Case (COMM_0) {
|
||||
Local0 = PID_GPIOCOM0
|
||||
}
|
||||
Case (COMM_1) {
|
||||
Local0 = PID_GPIOCOM1
|
||||
}
|
||||
Case (COMM_3) {
|
||||
Local0 = PID_GPIOCOM3
|
||||
}
|
||||
Case (COMM_4) {
|
||||
Local0 = PID_GPIOCOM4
|
||||
}
|
||||
Case (COMM_5) {
|
||||
Local0 = PID_GPIOCOM5
|
||||
}
|
||||
Default {
|
||||
Return (0)
|
||||
}
|
||||
}
|
||||
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
/* GPIO Power Management bits */
|
||||
Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0})
|
||||
|
||||
/*
|
||||
* Save GPIO Power Management bits
|
||||
*/
|
||||
Method (SGPM, 0, Serialized)
|
||||
{
|
||||
For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
|
||||
{
|
||||
Local1 = GPID (Local0)
|
||||
GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG)
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Restore GPIO Power Management bits
|
||||
*/
|
||||
Method (RGPM, 0, Serialized)
|
||||
{
|
||||
For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
|
||||
{
|
||||
CGPM (Local0, DerefOf(GPMB[Local0]))
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Save current setting of GPIO Power Management bits and
|
||||
* enable all Power Management bits for all communities
|
||||
*/
|
||||
Method (EGPM, 0, Serialized)
|
||||
{
|
||||
/* Save current setting and will restore it when resuming */
|
||||
SGPM ()
|
||||
/* Enable PM bits */
|
||||
For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
|
||||
{
|
||||
CGPM (Local0, MISCCFG_GPIO_PM_CONFIG_BITS)
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* GPIO _CRS
|
||||
* Returns Interrupt and memory resources required for GPIO controller
|
||||
*
|
||||
* Arg0 - GPIO Port ID Offset for given community
|
||||
*/
|
||||
Method (GCRS, 0x1, Serialized) {
|
||||
Name (RBFL,ResourceTemplate() {
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) {
|
||||
GPIO_IRQ14
|
||||
}
|
||||
QWordMemory (
|
||||
ResourceConsumer, ,
|
||||
MinFixed,
|
||||
MaxFixed,
|
||||
NonCacheable,
|
||||
ReadWrite,
|
||||
0x0, /* AddressGranularity */
|
||||
0x0000000000000000, /* AddressMinimum _MIN */
|
||||
0x000000000000FFFF, /* AddressMaximum _MAX */
|
||||
0x0, /* AddressTranslation */
|
||||
GPIO_BASE_SIZE, /* RangeLength _LEN */
|
||||
, ,
|
||||
RBL0,
|
||||
AddressRangeMemory,
|
||||
)
|
||||
})
|
||||
CreateQWordField (RBFL, RBL0._MIN, CML0)
|
||||
CreateQWordField (RBFL, RBL0._MAX, CMX0)
|
||||
CML0 = PCRB (Arg0)
|
||||
CMX0 = CML0 + GPIO_BASE_SIZE - 1
|
||||
Return (RBFL)
|
||||
}
|
||||
|
||||
/* GPIO Community 0: GPP_V, GPP_C */
|
||||
Device (GPI0)
|
||||
{
|
||||
Name (_HID, ACPI_GPIO_HID)
|
||||
Name (_CID, ACPI_GPIO_CID)
|
||||
Name (_UID, GPP_COMM0_ID)
|
||||
Name (_DDN, "GPIO Controller 0")
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Return (^^GCRS (PID_GPIOCOM0))
|
||||
}
|
||||
|
||||
Name (_DSD, Package (0x04)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x08)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-sw-revision",
|
||||
GPIO_SW_REVISION
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-community-name",
|
||||
GPP_COMM0_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-count",
|
||||
NUM_COM0_GROUPS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-ownership-offset",
|
||||
PAD_OWN_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-configuration-lock-offset",
|
||||
PAD_CFG_LOCK_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-host-software-pad-ownership-offset",
|
||||
HOSTSW_OWN_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-gpi-interrupt-status-offset",
|
||||
GPI_INT_STS_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-gpi-interrupt-enable-offset",
|
||||
GPI_INT_EN_0
|
||||
}
|
||||
},
|
||||
|
||||
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
|
||||
Package (0x02)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-0-subproperties",
|
||||
GPPV
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-1-subproperties",
|
||||
GPPC
|
||||
}
|
||||
}
|
||||
})
|
||||
|
||||
/* first bank/group in community 0: GPP_V */
|
||||
Name (GPPV, Package (0x02)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-name",
|
||||
GPP_V_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-count",
|
||||
NUM_GRP_V_PADS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-offset",
|
||||
GPP_V_START_OFFSET
|
||||
}
|
||||
}
|
||||
})
|
||||
|
||||
/* 2nd bank/group in community 0: GPP_C */
|
||||
Name (GPPC, Package (0x02)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-name",
|
||||
GPP_C_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-count",
|
||||
NUM_GRP_C_PADS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-offset",
|
||||
GPP_C_START_OFFSET
|
||||
}
|
||||
}
|
||||
})
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
}
|
||||
|
||||
/* GPIO Community 1: GPP_F, GPP_E */
|
||||
Device (GPI1)
|
||||
{
|
||||
Name (_HID, ACPI_GPIO_HID)
|
||||
Name (_CID, ACPI_GPIO_CID)
|
||||
Name (_UID, GPP_COMM1_ID)
|
||||
Name (_DDN, "GPIO Controller 1")
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Return (^^GCRS (PID_GPIOCOM1))
|
||||
}
|
||||
|
||||
Name (_DSD, Package (0x04)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x08)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-sw-revision",
|
||||
GPIO_SW_REVISION
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-community-name",
|
||||
GPP_COMM1_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-count",
|
||||
NUM_COM1_GROUPS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-ownership-offset",
|
||||
PAD_OWN_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-configuration-lock-offset",
|
||||
PAD_CFG_LOCK_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-host-software-pad-ownership-offset",
|
||||
HOSTSW_OWN_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-gpi-interrupt-status-offset",
|
||||
GPI_INT_STS_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-gpi-interrupt-enable-offset",
|
||||
GPI_INT_EN_0
|
||||
}
|
||||
},
|
||||
|
||||
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
|
||||
Package (0x02)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-0-subproperties",
|
||||
GPPF
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-1-subproperties",
|
||||
GPPE
|
||||
},
|
||||
|
||||
}
|
||||
})
|
||||
/* first bank/group in community 1: GPP_F */
|
||||
Name (GPPF, Package (0x02)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-name",
|
||||
GPP_F_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-count",
|
||||
NUM_GRP_F_PADS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-offset",
|
||||
GPP_F_START_OFFSET
|
||||
}
|
||||
}
|
||||
})
|
||||
/* 2nd bank/group in community 1: GPP_E */
|
||||
Name (GPPE, Package (0x02)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-name",
|
||||
GPP_E_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-count",
|
||||
NUM_GRP_E_PADS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-offset",
|
||||
GPP_E_START_OFFSET
|
||||
}
|
||||
}
|
||||
})
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
}
|
||||
|
||||
/* GPIO Community 3: CPUJTAG, GPP_H, GPP_A, VGPIO3 */
|
||||
Device (GPI3)
|
||||
{
|
||||
Name (_HID, ACPI_GPIO_HID)
|
||||
Name (_CID, ACPI_GPIO_CID)
|
||||
Name (_UID, GPP_COMM3_ID)
|
||||
Name (_DDN, "GPIO Controller 2")
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Return (^^GCRS (PID_GPIOCOM3))
|
||||
}
|
||||
|
||||
Name (_DSD, Package (0x04)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x08)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-sw-revision",
|
||||
GPIO_SW_REVISION
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-community-name",
|
||||
GPP_COMM3_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-count",
|
||||
NUM_COM3_GROUPS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-ownership-offset",
|
||||
PAD_OWN_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-configuration-lock-offset",
|
||||
PAD_CFG_LOCK_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-host-software-pad-ownership-offset",
|
||||
HOSTSW_OWN_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-gpi-interrupt-status-offset",
|
||||
GPI_INT_STS_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-gpi-interrupt-enable-offset",
|
||||
GPI_INT_EN_0
|
||||
}
|
||||
},
|
||||
|
||||
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
|
||||
Package (0x04)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-0-subproperties",
|
||||
JTAG
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-1-subproperties",
|
||||
GPPH
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-2-subproperties",
|
||||
GPPA
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-3-subproperties",
|
||||
VGP3
|
||||
}
|
||||
}
|
||||
})
|
||||
/* first bank/group in community 3: CPUJTAG */
|
||||
Name (JTAG, Package (0x02)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-name",
|
||||
GPP_CPUJTAG_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-count",
|
||||
NUM_GRP_CPUJTAG_PADS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-offset",
|
||||
GPP_CPUJTAG_START_OFFSET
|
||||
}
|
||||
}
|
||||
})
|
||||
/* 2nd bank/group in community 3: GPP_H */
|
||||
Name (GPPH, Package (0x02)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-name",
|
||||
GPP_H_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-count",
|
||||
NUM_GRP_H_PADS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-offset",
|
||||
GPP_H_START_OFFSET
|
||||
}
|
||||
}
|
||||
})
|
||||
|
||||
/* 3rd bank/group in community 3: GPP_A */
|
||||
Name (GPPA, Package (0x02)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-name",
|
||||
GPP_A_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-count",
|
||||
NUM_GRP_A_PADS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-offset",
|
||||
GPP_A_START_OFFSET
|
||||
}
|
||||
}
|
||||
})
|
||||
|
||||
/* 4th bank/group in community 3: VGPIO3 */
|
||||
Name (VGP3, Package (0x02)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-name",
|
||||
GPP_VGPIO3_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-count",
|
||||
NUM_GRP_VGPIO3_PADS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-offset",
|
||||
GPP_VGPIO3_START_OFFSET
|
||||
}
|
||||
}
|
||||
})
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
}
|
||||
|
||||
/* GPIO Community 4: GPP_S */
|
||||
Device (GPI4)
|
||||
{
|
||||
Name (_HID, ACPI_GPIO_HID)
|
||||
Name (_CID, ACPI_GPIO_CID)
|
||||
Name (_UID, GPP_COMM4_ID)
|
||||
Name (_DDN, "GPIO Controller 3")
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Return (^^GCRS (PID_GPIOCOM4))
|
||||
}
|
||||
|
||||
Name (_DSD, Package (0x04)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x08)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-sw-revision",
|
||||
GPIO_SW_REVISION
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-community-name",
|
||||
GPP_COMM4_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-count",
|
||||
NUM_COM4_GROUPS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-ownership-offset",
|
||||
PAD_OWN_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-configuration-lock-offset",
|
||||
PAD_CFG_LOCK_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-host-software-pad-ownership-offset",
|
||||
HOSTSW_OWN_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-gpi-interrupt-status-offset",
|
||||
GPI_INT_STS_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-gpi-interrupt-enable-offset",
|
||||
GPI_INT_EN_0
|
||||
}
|
||||
},
|
||||
|
||||
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
|
||||
Package (0x01)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-0-subproperties",
|
||||
GPPS
|
||||
}
|
||||
}
|
||||
})
|
||||
/* only bank/group in community 4: GPP_S */
|
||||
Name (GPPS, Package (0x02)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-name",
|
||||
GPP_S_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-count",
|
||||
NUM_GRP_S_PADS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-offset",
|
||||
GPP_S_START_OFFSET
|
||||
}
|
||||
}
|
||||
})
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
}
|
||||
|
||||
/* GPIO Community 5: GPP_B, GPP_D, VGPIO */
|
||||
Device (GPI5)
|
||||
{
|
||||
Name (_HID, ACPI_GPIO_HID)
|
||||
Name (_CID, ACPI_GPIO_CID)
|
||||
Name (_UID, GPP_COMM5_ID)
|
||||
Name (_DDN, "GPIO Controller 4")
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Return (^^GCRS (PID_GPIOCOM5))
|
||||
}
|
||||
|
||||
Name (_DSD, Package (0x04)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x08)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-sw-revision",
|
||||
GPIO_SW_REVISION
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-community-name",
|
||||
GPP_COMM5_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-count",
|
||||
NUM_COM5_GROUPS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-ownership-offset",
|
||||
// 0xD0
|
||||
PAD_OWN_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-configuration-lock-offset",
|
||||
PAD_CFG_LOCK_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-host-software-pad-ownership-offset",
|
||||
HOSTSW_OWN_REG_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-gpi-interrupt-status-offset",
|
||||
GPI_INT_STS_0
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-gpi-interrupt-enable-offset",
|
||||
GPI_INT_EN_0
|
||||
}
|
||||
},
|
||||
|
||||
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-0-subproperties",
|
||||
GPPB
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-1-subproperties",
|
||||
GPPD
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-2-subproperties",
|
||||
VGP0
|
||||
}
|
||||
}
|
||||
})
|
||||
/* first bank/group in community 5: GPP_B */
|
||||
Name (GPPB, Package (0x02)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-name",
|
||||
GPP_B_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-count",
|
||||
NUM_GRP_B_PADS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-offset",
|
||||
GPP_B_START_OFFSET
|
||||
}
|
||||
}
|
||||
})
|
||||
/* 2nd bank/group in community 5: GPP_D */
|
||||
Name (GPPD, Package (0x02)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-name",
|
||||
GPP_D_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-count",
|
||||
NUM_GRP_D_PADS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-offset",
|
||||
GPP_D_START_OFFSET
|
||||
}
|
||||
}
|
||||
})
|
||||
/* 3rd bank/group in community 5: VGPIO */
|
||||
Name (VGP0, Package (0x02)
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package (0x03)
|
||||
{
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-name",
|
||||
GPP_VGPIO_NAME
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-pad-count",
|
||||
NUM_GRP_VGPIO_PADS
|
||||
},
|
||||
|
||||
Package (0x02)
|
||||
{
|
||||
"intc-gpio-group-offset",
|
||||
GPP_VGPIO_START_OFFSET
|
||||
}
|
||||
}
|
||||
})
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
}
|
||||
13
src/soc/intel/pantherlake/acpi/hda.asl
Normal file
13
src/soc/intel/pantherlake/acpi/hda.asl
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Audio Controller - Device 31, Function 3 */
|
||||
|
||||
Device (HDAS)
|
||||
{
|
||||
Name (_ADR, 0x001f0003)
|
||||
Name (_DDN, "Audio Controller")
|
||||
Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
|
||||
|
||||
/* Device is D3 wake capable */
|
||||
Name (_S0W, 3)
|
||||
}
|
||||
303
src/soc/intel/pantherlake/acpi/pcie.asl
Normal file
303
src/soc/intel/pantherlake/acpi/pcie.asl
Normal file
|
|
@ -0,0 +1,303 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Intel PCH PCIe support */
|
||||
|
||||
Method (IRQM, 1, Serialized) {
|
||||
|
||||
/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
|
||||
Name (IQAA, Package () {
|
||||
Package () { 0x0000ffff, 0, 0, 16 },
|
||||
Package () { 0x0000ffff, 1, 0, 17 },
|
||||
Package () { 0x0000ffff, 2, 0, 18 },
|
||||
Package () { 0x0000ffff, 3, 0, 19 } })
|
||||
Name (IQAP, Package () {
|
||||
Package () { 0x0000ffff, 0, 0, 11 },
|
||||
Package () { 0x0000ffff, 1, 0, 10 },
|
||||
Package () { 0x0000ffff, 2, 0, 11 },
|
||||
Package () { 0x0000ffff, 3, 0, 11 } })
|
||||
|
||||
/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
|
||||
Name (IQBA, Package () {
|
||||
Package () { 0x0000ffff, 0, 0, 17 },
|
||||
Package () { 0x0000ffff, 1, 0, 18 },
|
||||
Package () { 0x0000ffff, 2, 0, 19 },
|
||||
Package () { 0x0000ffff, 3, 0, 16 } })
|
||||
Name (IQBP, Package () {
|
||||
Package () { 0x0000ffff, 0, 0, 10 },
|
||||
Package () { 0x0000ffff, 1, 0, 11 },
|
||||
Package () { 0x0000ffff, 2, 0, 11 },
|
||||
Package () { 0x0000ffff, 3, 0, 11 } })
|
||||
|
||||
/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
|
||||
Name (IQCA, Package () {
|
||||
Package () { 0x0000ffff, 0, 0, 18 },
|
||||
Package () { 0x0000ffff, 1, 0, 19 },
|
||||
Package () { 0x0000ffff, 2, 0, 16 },
|
||||
Package () { 0x0000ffff, 3, 0, 17 } })
|
||||
Name (IQCP, Package () {
|
||||
Package () { 0x0000ffff, 0, 0, 11 },
|
||||
Package () { 0x0000ffff, 1, 0, 11 },
|
||||
Package () { 0x0000ffff, 2, 0, 11 },
|
||||
Package () { 0x0000ffff, 3, 0, 10 } })
|
||||
|
||||
/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
|
||||
Name (IQDA, Package () {
|
||||
Package () { 0x0000ffff, 0, 0, 19 },
|
||||
Package () { 0x0000ffff, 1, 0, 16 },
|
||||
Package () { 0x0000ffff, 2, 0, 17 },
|
||||
Package () { 0x0000ffff, 3, 0, 18 } })
|
||||
Name (IQDP, Package () {
|
||||
Package () { 0x0000ffff, 0, 0, 11 },
|
||||
Package () { 0x0000ffff, 1, 0, 11 },
|
||||
Package () { 0x0000ffff, 2, 0, 10 },
|
||||
Package () { 0x0000ffff, 3, 0, 11 } })
|
||||
|
||||
Switch (ToInteger (Arg0))
|
||||
{
|
||||
Case (Package () { 1, 5, 9, 13 }) {
|
||||
If (PICM) {
|
||||
Return (IQAA)
|
||||
} Else {
|
||||
Return (IQAP)
|
||||
}
|
||||
}
|
||||
|
||||
Case (Package () { 2, 6, 10, 14 }) {
|
||||
If (PICM) {
|
||||
Return (IQBA)
|
||||
} Else {
|
||||
Return (IQBP)
|
||||
}
|
||||
}
|
||||
|
||||
Case (Package () { 3, 7, 11, 15 }) {
|
||||
If (PICM) {
|
||||
Return (IQCA)
|
||||
} Else {
|
||||
Return (IQCP)
|
||||
}
|
||||
}
|
||||
|
||||
Case (Package () { 4, 8, 12, 16 }) {
|
||||
If (PICM) {
|
||||
Return (IQDA)
|
||||
} Else {
|
||||
Return (IQDP)
|
||||
}
|
||||
}
|
||||
|
||||
Default {
|
||||
If (PICM) {
|
||||
Return (IQDA)
|
||||
} Else {
|
||||
Return (IQDP)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP01)
|
||||
{
|
||||
Name (_ADR, 0x001C0000)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP02)
|
||||
{
|
||||
Name (_ADR, 0x001C0001)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP03)
|
||||
{
|
||||
Name (_ADR, 0x001C0002)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP04)
|
||||
{
|
||||
Name (_ADR, 0x001C0003)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP05)
|
||||
{
|
||||
Name (_ADR, 0x001C0004)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP06)
|
||||
{
|
||||
Name (_ADR, 0x001C0005)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP07)
|
||||
{
|
||||
Name (_ADR, 0x001C0006)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP08)
|
||||
{
|
||||
Name (_ADR, 0x001C0007)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP09)
|
||||
{
|
||||
Name (_ADR, 0x00060000)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP10)
|
||||
{
|
||||
Name (_ADR, 0x00060001)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
#if CONFIG(SOC_INTEL_PANTHERLAKE_H)
|
||||
Device (RP11)
|
||||
{
|
||||
Name (_ADR, 0x00060002)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
|
||||
Device (RP12)
|
||||
{
|
||||
Name (_ADR, 0x00060003)
|
||||
|
||||
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
|
||||
Field (RPCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
, 24,
|
||||
RPPN, 8, /* Root Port Number */
|
||||
}
|
||||
|
||||
Method (_PRT)
|
||||
{
|
||||
Return (IRQM (RPPN))
|
||||
}
|
||||
}
|
||||
#endif
|
||||
81
src/soc/intel/pantherlake/acpi/serialio.asl
Normal file
81
src/soc/intel/pantherlake/acpi/serialio.asl
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Intel Serial IO Devices */
|
||||
|
||||
Device (I2C0)
|
||||
{
|
||||
Name (_ADR, 0x00150000)
|
||||
Name (_DDN, "Serial IO I2C Controller 0")
|
||||
}
|
||||
|
||||
Device (I2C1)
|
||||
{
|
||||
Name (_ADR, 0x00150001)
|
||||
Name (_DDN, "Serial IO I2C Controller 1")
|
||||
}
|
||||
|
||||
Device (I2C2)
|
||||
{
|
||||
Name (_ADR, 0x00150002)
|
||||
Name (_DDN, "Serial IO I2C Controller 2")
|
||||
}
|
||||
|
||||
Device (I2C3)
|
||||
{
|
||||
Name (_ADR, 0x00150003)
|
||||
Name (_DDN, "Serial IO I2C Controller 3")
|
||||
}
|
||||
|
||||
Device (I2C4)
|
||||
{
|
||||
Name (_ADR, 0x00190000)
|
||||
Name (_DDN, "Serial IO I2C Controller 4")
|
||||
}
|
||||
|
||||
Device (I2C5)
|
||||
{
|
||||
Name (_ADR, 0x00190001)
|
||||
Name (_DDN, "Serial IO I2C Controller 5")
|
||||
}
|
||||
|
||||
Device (FSPI)
|
||||
{
|
||||
Name (_ADR, 0x001f0005)
|
||||
Name (_DDN, "Fast SPI")
|
||||
}
|
||||
|
||||
Device (SPI0)
|
||||
{
|
||||
Name (_ADR, 0x001e0002)
|
||||
Name (_DDN, "Serial IO SPI Controller 0")
|
||||
}
|
||||
|
||||
Device (SPI1)
|
||||
{
|
||||
Name (_ADR, 0x001e0003)
|
||||
Name (_DDN, "Serial IO SPI Controller 1")
|
||||
}
|
||||
|
||||
Device (SPI2)
|
||||
{
|
||||
Name (_ADR, 0x00120006)
|
||||
Name (_DDN, "Serial IO SPI Controller 2")
|
||||
}
|
||||
|
||||
Device (UAR0)
|
||||
{
|
||||
Name (_ADR, 0x001e0000)
|
||||
Name (_DDN, "Serial IO UART Controller 0")
|
||||
}
|
||||
|
||||
Device (UAR1)
|
||||
{
|
||||
Name (_ADR, 0x001e0001)
|
||||
Name (_DDN, "Serial IO UART Controller 1")
|
||||
}
|
||||
|
||||
Device (UAR2)
|
||||
{
|
||||
Name (_ADR, 0x00190002)
|
||||
Name (_DDN, "Serial IO UART Controller 2")
|
||||
}
|
||||
54
src/soc/intel/pantherlake/acpi/southbridge.asl
Normal file
54
src/soc/intel/pantherlake/acpi/southbridge.asl
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <intelblocks/itss.h>
|
||||
#include <intelblocks/pcr.h>
|
||||
#include <soc/pcr_ids.h>
|
||||
|
||||
/* PCR access */
|
||||
#include <soc/intel/common/acpi/pch_pcr.asl>
|
||||
/* IOE PCR access */
|
||||
#include <soc/intel/common/acpi/ioe_pcr.asl>
|
||||
|
||||
/* PCIE src clock control */
|
||||
#include <soc/intel/common/acpi/pcie_clk.asl>
|
||||
|
||||
/* PCH clock */
|
||||
#include "camera_clock_ctl.asl"
|
||||
|
||||
/* GPIO controller */
|
||||
#include "gpio.asl"
|
||||
|
||||
/* ESPI 0:1f.0 */
|
||||
#include <soc/intel/common/block/acpi/acpi/lpc.asl>
|
||||
|
||||
/* PCH HDA */
|
||||
#include "hda.asl"
|
||||
|
||||
/* PCIE Ports */
|
||||
#include "pcie.asl"
|
||||
|
||||
/* Serial IO */
|
||||
#include "serialio.asl"
|
||||
|
||||
/* SMBus 0:1f.4 */
|
||||
#include <soc/intel/common/block/acpi/acpi/smbus.asl>
|
||||
|
||||
/* ISH 0:12.0 */
|
||||
#if CONFIG(DRIVERS_INTEL_ISH)
|
||||
#include <soc/intel/common/block/acpi/acpi/ish.asl>
|
||||
#endif
|
||||
|
||||
/* USB XHCI 0:14.0 */
|
||||
#include "xhci.asl"
|
||||
|
||||
/* PCI _OSC */
|
||||
#include <soc/intel/common/acpi/pci_osc.asl>
|
||||
|
||||
/* GbE 0:1f.6 */
|
||||
#if CONFIG(MAINBOARD_USES_IFD_GBE_REGION)
|
||||
#include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
|
||||
|
||||
/* UFS 0:17:0 */
|
||||
/* TODO: Add ufs.asl entry for PTL-U SKU */
|
||||
|
||||
#endif
|
||||
822
src/soc/intel/pantherlake/acpi/tcss.asl
Normal file
822
src/soc/intel/pantherlake/acpi/tcss.asl
Normal file
|
|
@ -0,0 +1,822 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <intelblocks/tcss.h>
|
||||
#include <soc/iomap.h>
|
||||
|
||||
/*
|
||||
* Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI),
|
||||
* USB device controller(xDCI), Thunderbolt DMA devices and Thunderbolt PCIe controllers.
|
||||
* PCIe RP0/RP1 is grouped with DMA0 and PCIe RP2/RP3 is grouped with DMA1.
|
||||
*/
|
||||
#define TCSS_TBT_PCIE0_RP0 0
|
||||
#define TCSS_TBT_PCIE0_RP1 1
|
||||
#define TCSS_TBT_PCIE0_RP2 2
|
||||
#define TCSS_TBT_PCIE0_RP3 3
|
||||
#define TCSS_XHCI 4
|
||||
#define TCSS_XDCI 5
|
||||
#define TCSS_DMA0 6
|
||||
#define TCSS_DMA1 7
|
||||
|
||||
/*
|
||||
* MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE
|
||||
* Command code 0x15
|
||||
* Description: Gateway command for handling TCSS DEVEN clear/restore.
|
||||
* Field PARAM1[15:8] of the _INTERFACE register is used in this command to select from
|
||||
* a pre-defined set of subcommands.
|
||||
*/
|
||||
#define MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE 0x00000015
|
||||
#define TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS 0 /* Sub-command 0 */
|
||||
#define TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ 1 /* Sub-command 1 */
|
||||
#define TCSS_IOM_ACK_TIMEOUT_IN_MS 100
|
||||
|
||||
#define MCHBAR_TCSS_DEVEN_OFFSET 0x73a8
|
||||
|
||||
#define REVISION_ID 1
|
||||
#define UNRECOGNIZED_UUID 0x4
|
||||
#define UNRECOGNIZED_REVISION 0x8
|
||||
|
||||
#define USB_TUNNELING 0x1
|
||||
#define DISPLAY_PORT_TUNNELING 0x2
|
||||
#define PCIE_TUNNELING 0x4
|
||||
#define INTER_DOMAIN_USB4_INTERNET_PROTOCOL 0x8
|
||||
|
||||
Scope (\_SB)
|
||||
{
|
||||
/* Device base address */
|
||||
Method (BASE, 1)
|
||||
{
|
||||
Local0 = Arg0 & 0x7 /* Function number */
|
||||
Local1 = (Arg0 >> 16) & 0x1F /* Device number */
|
||||
Local2 = (Local0 << 12) + (Local1 << 15)
|
||||
Local3 = \_SB.PCI0.GPCB() + Local2
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
/*
|
||||
* Define PCH ACPIBASE IO as an ACPI operating region. The base address can be
|
||||
* found in Device 31, Function 2, Offset 40h.
|
||||
*/
|
||||
OperationRegion (PMIO, SystemIO, ACPI_BASE_ADDRESS, 0x80)
|
||||
Field (PMIO, ByteAcc, NoLock, Preserve) {
|
||||
Offset(0x6c), /* 0x6C, General Purpose Event 0 Status [127:96] */
|
||||
, 19,
|
||||
CPWS, 1, /* CPU WAKE STATUS */
|
||||
Offset(0x7c), /* 0x7C, General Purpose Event 0 Enable [127:96] */
|
||||
, 19,
|
||||
CPWE, 1 /* CPU WAKE EN */
|
||||
}
|
||||
|
||||
Name (C2PW, 0) /* Set default value to 0. */
|
||||
|
||||
/*
|
||||
* C2PM (CPU to PCH Method)
|
||||
*
|
||||
* This object is Enable/Disable GPE_CPU_WAKE_EN.
|
||||
* Arguments: (4)
|
||||
* Arg0 - An Integer containing the device wake capability
|
||||
* Arg1 - An Integer containing the target system state
|
||||
* Arg2 - An Integer containing the target device state
|
||||
* Arg3 - An Integer containing the request device type
|
||||
* Return Value:
|
||||
* return 0
|
||||
*/
|
||||
Method (C2PM, 4, NotSerialized)
|
||||
{
|
||||
Local0 = 1 << Arg3
|
||||
/* This method is used to enable/disable wake from Tcss Device (WKEN). */
|
||||
If (Arg0 && Arg1)
|
||||
{ /* If entering Sx and enabling wake, need to enable WAKE capability. */
|
||||
If (CPWE == 0) { /* If CPU WAKE EN is not set, Set it. */
|
||||
If (CPWS) { /* If CPU WAKE STATUS is set, Clear it. */
|
||||
/* Clear CPU WAKE STATUS by writing 1. */
|
||||
CPWS = 1
|
||||
}
|
||||
CPWE = 1 /* Set CPU WAKE EN by writing 1. */
|
||||
}
|
||||
If ((C2PW & Local0) == 0) {
|
||||
/* Set Corresponding Device En BIT in C2PW. */
|
||||
C2PW |= Local0
|
||||
}
|
||||
} Else { /* If Staying in S0 or Disabling Wake. */
|
||||
If (Arg0 || Arg2) { /* Check if Exiting D0 and arming for wake. */
|
||||
/* If CPU WAKE EN is not set, Set it. */
|
||||
If (CPWE == 0) {
|
||||
/* If CPU WAKE STATUS is set, Clear it. */
|
||||
If (CPWS) {
|
||||
/* Clear CPU WAKE STATUS by writing 1. */
|
||||
CPWS = 1
|
||||
}
|
||||
CPWE = 1 /* Set CPU WAKE EN by writing 1. */
|
||||
}
|
||||
If ((C2PW & Local0) == 0) {
|
||||
/* Set Corresponding Device En BIT in C2PW. */
|
||||
C2PW |= Local0
|
||||
}
|
||||
} Else {
|
||||
/*
|
||||
* Disable runtime PME, either because staying in D0 or
|
||||
* disabling wake.
|
||||
*/
|
||||
If ((C2PW & Local0) != 0) {
|
||||
/*
|
||||
* Clear Corresponding Device En BIT in C2PW.
|
||||
*/
|
||||
C2PW &= ~Local0
|
||||
}
|
||||
If ((CPWE != 0) && (C2PW == 0)) {
|
||||
/*
|
||||
* If CPU WAKE EN is set, Clear it. Clear CPU WAKE EN
|
||||
* by writing 0.
|
||||
*/
|
||||
CPWE = 0
|
||||
}
|
||||
}
|
||||
}
|
||||
Return (0)
|
||||
}
|
||||
|
||||
Method (_OSC, 4, Serialized)
|
||||
{
|
||||
CreateDWordField (Arg3, 0, CDW1)
|
||||
If (Arg0 == ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")) {
|
||||
/* Platform-Wide _OSC Capabilities
|
||||
* Arg0: UUID = {0811B06E-4A27-44F9-8D60-3CBBC22E7B48}
|
||||
* Arg1: Revision ID = 1
|
||||
* Arg2: Count of entries (DWORD) in Arge3 (Integer): 3
|
||||
* Arg3: DWORD capabilities buffer:
|
||||
* First DWORD: The standard definition bits are used to return errors.
|
||||
* Second DWORD: See ACPI specification Platform-Wide _OSC Capabilities
|
||||
* DWORD2 table for Bits 0-17. Bit 18 is newly defined as native USB4
|
||||
* support. The OS sets this bit to indicate support for an OSPM-native
|
||||
* USB4 Connection Manager which handles USB4 connection events and
|
||||
* link management.
|
||||
*/
|
||||
If (Arg1 != REVISION_ID) {
|
||||
CDW1 |= UNRECOGNIZED_REVISION
|
||||
}
|
||||
Return (Arg3)
|
||||
#if CONFIG(SOFTWARE_CONNECTION_MANAGER)
|
||||
/*
|
||||
* Software Connection Manager doesn't work with Linux 5.13 or later and
|
||||
* results in TBT ports timing out. Not advertising this results in
|
||||
* Firmware Connection Manager being used and TBT works correctly.
|
||||
*/
|
||||
} ElseIf (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) {
|
||||
/*
|
||||
* Operating System Capabilities for USB4
|
||||
* Arg0: UUID = {23A0D13A-26AB-486C-9C5F-0FFA525A575A}
|
||||
* Arg1: Revision ID = 1
|
||||
* Arg2: Count of entries (DWORD) in Arg3 (Integer): 3
|
||||
* Arg3: DWORD capabilities buffer:
|
||||
* First DWORD: The standard definition bits are used to return errors.
|
||||
* Second DWORD: OSPM support field for USB4, bits [31:0] reserved.
|
||||
* Third DWORD: OSPM control field for USB4.
|
||||
* bit 0: USB tunneling
|
||||
* bit 1: DisplayPort tunneling
|
||||
* bit 2: PCIe tunneling
|
||||
* bit 3: Inter-domain USB4 internet protocol
|
||||
* bit 31:4: reserved
|
||||
* Return: The platform acknowledges the capabilities buffer by
|
||||
* returning a buffer of DWORD of the same length. Masked/Cleared bits
|
||||
* in the control field indicate that the platform does not permit OSPM
|
||||
* control of the respectively capabilities or features.
|
||||
*/
|
||||
CreateDWordField (Arg3, 8, CDW3)
|
||||
Local0 = CDW3
|
||||
|
||||
If (Arg1 != REVISION_ID) {
|
||||
CDW1 |= UNRECOGNIZED_REVISION
|
||||
Return (Arg3)
|
||||
}
|
||||
Local0 |= USB_TUNNELING | DISPLAY_PORT_TUNNELING | PCIE_TUNNELING |
|
||||
INTER_DOMAIN_USB4_INTERNET_PROTOCOL
|
||||
CDW3 = Local0
|
||||
Return (Arg3)
|
||||
#endif
|
||||
} Else {
|
||||
CDW1 |= UNRECOGNIZED_UUID
|
||||
Return (Arg3)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Scope (_GPE)
|
||||
{
|
||||
/* TCSS PCI Express Hot-Plug wake event */
|
||||
Method (_L77, 0, NotSerialized)
|
||||
{
|
||||
/*
|
||||
* Delay for 100ms to meet the timing requirements of the PCI Express Base
|
||||
* Specification, Revision 1.0A, Section 6.6 ("...software must wait at least
|
||||
* 100ms from the end of reset of one or more device before it is permitted
|
||||
* to issue Configuration Requests to those devices").
|
||||
*/
|
||||
Sleep (100)
|
||||
|
||||
If (CondRefOf (\_SB.PCI0.TXHC)) {
|
||||
/* Invoke PCIe root ports wake event handler */
|
||||
\_SB.PCI0.TRP0.HPEV()
|
||||
\_SB.PCI0.TRP1.HPEV()
|
||||
\_SB.PCI0.TRP2.HPEV()
|
||||
\_SB.PCI0.TRP3.HPEV()
|
||||
}
|
||||
|
||||
/* Check Root Port 0 for a Hot Plug Event if the port is enabled */
|
||||
If (((\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP0.HPSX)) {
|
||||
If (\_SB.PCI0.TRP0.PDCX) {
|
||||
/* Clear all status bits */
|
||||
\_SB.PCI0.TRP0.PDCX = 1
|
||||
\_SB.PCI0.TRP0.HPSX = 1
|
||||
/*
|
||||
* Intercept Presence Detect Changed interrupt and make sure
|
||||
* the L0s is disabled on empty slots.
|
||||
*/
|
||||
If (!\_SB.PCI0.TRP0.PDSX) {
|
||||
/*
|
||||
* The PCIe slot is empty, so disable L0s on hot unplug.
|
||||
*/
|
||||
\_SB.PCI0.TRP0.L0SE = 0
|
||||
}
|
||||
/* Performs proper notification to the OS. */
|
||||
Notify (\_SB.PCI0.TRP0, 0)
|
||||
} Else {
|
||||
/* False event. Clear Hot-Plug status, then exit. */
|
||||
\_SB.PCI0.TRP0.HPSX = 1
|
||||
}
|
||||
}
|
||||
|
||||
/* Check Root Port 1 for a Hot Plug Event if the port is enabled */
|
||||
If (((\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP1.HPSX)) {
|
||||
If (\_SB.PCI0.TRP1.PDCX) {
|
||||
\_SB.PCI0.TRP1.PDCX = 1
|
||||
\_SB.PCI0.TRP1.HPSX = 1
|
||||
If (!\_SB.PCI0.TRP1.PDSX) {
|
||||
\_SB.PCI0.TRP1.L0SE = 0
|
||||
}
|
||||
Notify (\_SB.PCI0.TRP1, 0)
|
||||
} Else {
|
||||
\_SB.PCI0.TRP1.HPSX = 1
|
||||
}
|
||||
}
|
||||
|
||||
/* Check Root Port 2 for a Hot Plug Event if the port is enabled */
|
||||
If (((\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP2.HPSX)) {
|
||||
If (\_SB.PCI0.TRP2.PDCX) {
|
||||
\_SB.PCI0.TRP2.PDCX = 1
|
||||
\_SB.PCI0.TRP2.HPSX = 1
|
||||
If (!\_SB.PCI0.TRP2.PDSX) {
|
||||
\_SB.PCI0.TRP2.L0SE = 0
|
||||
}
|
||||
Notify (\_SB.PCI0.TRP2, 0)
|
||||
} Else {
|
||||
\_SB.PCI0.TRP2.HPSX = 1
|
||||
}
|
||||
}
|
||||
|
||||
/* Check Root Port 3 for a Hot Plug Event if the port is enabled */
|
||||
If (((\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP3.HPSX)) {
|
||||
If (\_SB.PCI0.TRP3.PDCX) {
|
||||
\_SB.PCI0.TRP3.PDCX = 1
|
||||
\_SB.PCI0.TRP3.HPSX = 1
|
||||
If (!\_SB.PCI0.TRP3.PDSX) {
|
||||
\_SB.PCI0.TRP3.L0SE = 0
|
||||
}
|
||||
Notify (\_SB.PCI0.TRP3, 0)
|
||||
} Else {
|
||||
\_SB.PCI0.TRP3.HPSX = 1
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* TCSS PCI Express power management event */
|
||||
Method (_L76, 0, Serialized)
|
||||
{
|
||||
If (CondRefOf (\_SB.PCI0.TXHC)) {
|
||||
If (\_SB.PCI0.TRP0.HPME() == 1) {
|
||||
Notify (\_SB.PCI0.TDM0, 0x2)
|
||||
Notify (\_SB.PCI0.TRP0, 0x2)
|
||||
}
|
||||
|
||||
If (\_SB.PCI0.TRP1.HPME() == 1) {
|
||||
Notify (\_SB.PCI0.TDM0, 0x2)
|
||||
Notify (\_SB.PCI0.TRP1, 0x2)
|
||||
}
|
||||
|
||||
If (\_SB.PCI0.TRP2.HPME() == 1) {
|
||||
Notify (\_SB.PCI0.TDM1, 0x2)
|
||||
Notify (\_SB.PCI0.TRP2, 0x2)
|
||||
}
|
||||
|
||||
If (\_SB.PCI0.TRP3.HPME() == 1) {
|
||||
Notify (\_SB.PCI0.TDM1, 0x2)
|
||||
Notify (\_SB.PCI0.TRP3, 0x2)
|
||||
}
|
||||
}
|
||||
|
||||
/* Invoke PCIe root ports power management status handler */
|
||||
\_SB.PCI0.TRP0.HPME()
|
||||
\_SB.PCI0.TRP1.HPME()
|
||||
\_SB.PCI0.TRP2.HPME()
|
||||
\_SB.PCI0.TRP3.HPME()
|
||||
}
|
||||
}
|
||||
|
||||
Scope (\_SB.PCI0)
|
||||
{
|
||||
Device (IOM)
|
||||
{
|
||||
Name (_HID, "INTC107A")
|
||||
Name (_DDN, "Intel(R) Panther Lake Input Output Manager(IOM) driver")
|
||||
/* IOM preserved MMIO range from 0x3fff0aa0000 to 0x3fff0aa15ff. */
|
||||
Name (_CRS, ResourceTemplate () {
|
||||
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
|
||||
NonCacheable, ReadWrite, 0x0,
|
||||
IOM_BASE_ADDR, IOM_BASE_ADDR_MAX, 0x0,
|
||||
IOM_BASE_SIZE,,,)
|
||||
})
|
||||
/* Hide the device so that Windows does not complain on missing driver */
|
||||
Name (_STA, 0xB)
|
||||
}
|
||||
|
||||
/*
|
||||
* Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset
|
||||
* 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR.
|
||||
*/
|
||||
OperationRegion (TDEN, SystemMemory, (GMHB() + MCHBAR_TCSS_DEVEN_OFFSET), 0x4)
|
||||
Field (TDEN, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
TRE0, 1, /* PCIE0_EN */
|
||||
TRE1, 1, /* PCIE1_EN */
|
||||
TRE2, 1, /* PCIE2_EN */
|
||||
TRE3, 1, /* PCIE3_EN */
|
||||
, 4,
|
||||
THCE, 1, /* XHCI_EN */
|
||||
TDCE, 1, /* XDCI_EN */
|
||||
DME0, 1, /* TBT_DMA0_EN */
|
||||
DME1, 1, /* TBT_DMA1_EN */
|
||||
, 20
|
||||
}
|
||||
|
||||
/*
|
||||
* Operation region defined to access the pCode mailbox interface. Get the MCHBAR
|
||||
* in offset 0x48 in B0:D0:F0. MMIO address is in offset 0x5DA0 of MCHBAR.
|
||||
*/
|
||||
OperationRegion (PBAR, SystemMemory, (GMHB() + 0x5DA0), 0x08)
|
||||
Field (PBAR, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
PMBD, 32, /* pCode MailBox Data, offset 0x5DA0 in MCHBAR */
|
||||
PMBC, 8, /* pCode MailBox Command, [7:0] of offset 0x5DA4 in MCHBAR */
|
||||
PSCM, 8, /* pCode MailBox Sub-Command, [15:8] of offset 0x5DA4 in MCHBAR */
|
||||
, 15, /* Reserved */
|
||||
PMBR, 1 /* pCode MailBox RunBit, [31:31] of offset 0x5DA4 in MCHBAR */
|
||||
}
|
||||
|
||||
/*
|
||||
* Poll pCode MailBox Ready
|
||||
*
|
||||
* Return 0xFF - Timeout
|
||||
* 0x00 - Ready
|
||||
*/
|
||||
Method (PMBY, 0)
|
||||
{
|
||||
Local0 = 0
|
||||
While (PMBR && (Local0 < 1000)) {
|
||||
Local0++
|
||||
Stall (1)
|
||||
}
|
||||
If (Local0 == 1000) {
|
||||
Printf("Timeout occurred.")
|
||||
Return (0xFF)
|
||||
}
|
||||
Return (0)
|
||||
}
|
||||
|
||||
|
||||
/* From RegBar Base, IOM_TypeC_SW_configuration_1 is at offset 0x40 */
|
||||
OperationRegion (IOMR, SystemMemory, IOM_BASE_ADDR, 0x100)
|
||||
Field (IOMR, DWordAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset(0x40),
|
||||
, 15,
|
||||
TD3C, 1, /* [15:15] Type C D3 cold bit */
|
||||
TACK, 1, /* [16:16] IOM Acknowledge bit */
|
||||
DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */
|
||||
/* display is OFF, clear otherwise */
|
||||
Offset(0x44), /* SW_CONFIG_2 */
|
||||
DPHD, 1, /* [0:0] DP_ALT and DP Tunneling HPD assertion */
|
||||
Offset(0x48), /* SW_CONFIG_3 */
|
||||
, 12,
|
||||
INDP, 1, /* [12:12] The capability of monitoring the DP_ALT and DP tunneling */
|
||||
Offset(0x70), /* Physical addr is offset 0x70. */
|
||||
IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */
|
||||
IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */
|
||||
}
|
||||
|
||||
/*
|
||||
* TBT Group0 ON method
|
||||
*/
|
||||
Method (TG0N, 0)
|
||||
{
|
||||
If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) {
|
||||
Printf("TDM0 does not exist.")
|
||||
} Else {
|
||||
If (\_SB.PCI0.TDM0.STAT == 0) {
|
||||
/* DMA0 is in D3Cold early. */
|
||||
\_SB.PCI0.TDM0.D3CX() /* RTD3 Exit */
|
||||
|
||||
Printf("Bring TBT RPs out of D3Code.")
|
||||
If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
|
||||
/* RP0 D3 cold exit. */
|
||||
\_SB.PCI0.TRP0.D3CX()
|
||||
}
|
||||
If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) {
|
||||
/* RP1 D3 cold exit. */
|
||||
\_SB.PCI0.TRP1.D3CX()
|
||||
}
|
||||
} Else {
|
||||
Printf("Drop TG0N due to it is already exit D3 cold.")
|
||||
}
|
||||
|
||||
/* TBT RTD3 exit 10ms delay. */
|
||||
Sleep (10)
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* TBT Group0 OFF method
|
||||
*/
|
||||
Method (TG0F, 0)
|
||||
{
|
||||
If (\_SB.PCI0.TDM0.VDID == 0xFFFFFFFF) {
|
||||
Printf("TDM0 does not exist.")
|
||||
} Else {
|
||||
If (\_SB.PCI0.TDM0.STAT == 1) {
|
||||
/* DMA0 is not in D3Cold now. */
|
||||
\_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */
|
||||
|
||||
Printf("Push TBT RPs to D3Cold together")
|
||||
If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
|
||||
/* Put RP0 to D3 cold. */
|
||||
\_SB.PCI0.TRP0.D3CE()
|
||||
}
|
||||
If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) {
|
||||
/* Put RP1 to D3 cold. */
|
||||
\_SB.PCI0.TRP1.D3CE()
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* TBT Group1 ON method
|
||||
*/
|
||||
Method (TG1N, 0)
|
||||
{
|
||||
If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) {
|
||||
Printf("TDM1 does not exist.")
|
||||
} Else {
|
||||
If (\_SB.PCI0.TDM1.STAT == 0) {
|
||||
/* DMA1 is in D3Cold early. */
|
||||
\_SB.PCI0.TDM1.D3CX() /* RTD3 Exit */
|
||||
|
||||
Printf("Bring TBT RPs out of D3Code.")
|
||||
If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
|
||||
/* RP2 D3 cold exit. */
|
||||
\_SB.PCI0.TRP2.D3CX()
|
||||
}
|
||||
If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) {
|
||||
/* RP3 D3 cold exit. */
|
||||
\_SB.PCI0.TRP3.D3CX()
|
||||
}
|
||||
} Else {
|
||||
Printf("Drop TG1N due to it is already exit D3 cold.")
|
||||
}
|
||||
|
||||
/* TBT RTD3 exit 10ms delay. */
|
||||
Sleep (10)
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* TBT Group1 OFF method
|
||||
*/
|
||||
Method (TG1F, 0)
|
||||
{
|
||||
If (\_SB.PCI0.TDM1.VDID == 0xFFFFFFFF) {
|
||||
Printf("TDM1 does not exist.")
|
||||
} Else {
|
||||
If (\_SB.PCI0.TDM1.STAT == 1) {
|
||||
/* DMA1 is not in D3Cold now */
|
||||
\_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */
|
||||
|
||||
Printf("Push TBT RPs to D3Cold together")
|
||||
If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
|
||||
/* Put RP2 to D3 cold. */
|
||||
\_SB.PCI0.TRP2.D3CE()
|
||||
}
|
||||
If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) {
|
||||
/* Put RP3 to D3 cold */
|
||||
\_SB.PCI0.TRP3.D3CE()
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
PowerResource (TBT0, 5, 1)
|
||||
{
|
||||
Method (_STA, 0)
|
||||
{
|
||||
Return (\_SB.PCI0.TDM0.STAT)
|
||||
}
|
||||
|
||||
Method (_ON, 0)
|
||||
{
|
||||
TG0N()
|
||||
}
|
||||
|
||||
Method (_OFF, 0)
|
||||
{
|
||||
If (\_SB.PCI0.TDM0.SD3C == 0) {
|
||||
TG0F()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
PowerResource (TBT1, 5, 1)
|
||||
{
|
||||
Method (_STA, 0)
|
||||
{
|
||||
Return (\_SB.PCI0.TDM1.STAT)
|
||||
}
|
||||
|
||||
Method (_ON, 0)
|
||||
{
|
||||
TG1N()
|
||||
}
|
||||
|
||||
Method (_OFF, 0)
|
||||
{
|
||||
If (\_SB.PCI0.TDM1.SD3C == 0) {
|
||||
TG1F()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if CONFIG(D3COLD_SUPPORT)
|
||||
Method (TCON, 0)
|
||||
{
|
||||
/* Reset IOM D3 cold bit if it is in D3 cold now. */
|
||||
If (TD3C == 1) /* It was in D3 cold before. */
|
||||
{
|
||||
/* Reset IOM D3 cold bit. */
|
||||
TD3C = 0 /* Request IOM for D3 cold exit sequence. */
|
||||
Local0 = 0 /* Time check counter variable */
|
||||
/* Wait for ack, the maximum wait time for the ack is 100 msec. */
|
||||
While ((TACK != 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) {
|
||||
/*
|
||||
* Wait in this loop until TACK becomes 0 with timeout
|
||||
* TCSS_IOM_ACK_TIMEOUT_IN_MS by default.
|
||||
*/
|
||||
Sleep (1) /* Delay of 1ms. */
|
||||
Local0++
|
||||
}
|
||||
|
||||
If (Local0 == TCSS_IOM_ACK_TIMEOUT_IN_MS) {
|
||||
Printf("Error: Timeout occurred.")
|
||||
}
|
||||
Else
|
||||
{
|
||||
Printf("TCSS D3 exit.");
|
||||
}
|
||||
}
|
||||
Else {
|
||||
Printf("Drop TCON due to it is already exit D3 cold.")
|
||||
}
|
||||
}
|
||||
|
||||
Method (TCOF, 0)
|
||||
{
|
||||
If ((\_SB.PCI0.TXHC.SD3C != 0) || (\_SB.PCI0.TDM0.SD3C != 0)
|
||||
|| (\_SB.PCI0.TDM1.SD3C != 0))
|
||||
{
|
||||
Printf("Skip D3C entry.")
|
||||
Return
|
||||
}
|
||||
|
||||
/* Request IOM for D3 cold entry sequence. */
|
||||
TD3C = 1
|
||||
}
|
||||
|
||||
PowerResource (D3C, 5, 0)
|
||||
{
|
||||
/*
|
||||
* Variable to save power state
|
||||
* 1 - TC Cold request cleared.
|
||||
* 0 - TC Cold request sent.
|
||||
*/
|
||||
Name (STAT, 0x1)
|
||||
|
||||
Method (_STA, 0)
|
||||
{
|
||||
Return (STAT)
|
||||
}
|
||||
|
||||
Method (_ON, 0)
|
||||
{
|
||||
\_SB.PCI0.TCON()
|
||||
STAT = 1
|
||||
}
|
||||
|
||||
Method (_OFF, 0)
|
||||
{
|
||||
\_SB.PCI0.TCOF()
|
||||
STAT = 0
|
||||
}
|
||||
}
|
||||
#endif // D3COLD_SUPPORT
|
||||
|
||||
/*
|
||||
* TCSS xHCI device
|
||||
*/
|
||||
Device (TXHC)
|
||||
{
|
||||
Name (_ADR, 0x000D0000)
|
||||
Name (_DDN, "North XHCI controller")
|
||||
Name (_STR, Unicode ("North XHCI controller"))
|
||||
Name (DCPM, TCSS_XHCI)
|
||||
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
If (THCE == 1) {
|
||||
Return (0x0F)
|
||||
} Else {
|
||||
Return (0x0)
|
||||
}
|
||||
}
|
||||
#include "tcss_xhci.asl"
|
||||
}
|
||||
|
||||
/*
|
||||
* TCSS DMA0 device
|
||||
*/
|
||||
Device (TDM0)
|
||||
{
|
||||
Name (_ADR, 0x000D0002)
|
||||
Name (_DDN, "TBT DMA0 controller")
|
||||
Name (_STR, Unicode ("TBT DMA0 controller"))
|
||||
Name (DUID, 0) /* TBT DMA number */
|
||||
Name (DCPM, TCSS_DMA0)
|
||||
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
If (DME0 == 1) {
|
||||
Return (0x0F)
|
||||
} Else {
|
||||
Return (0x0)
|
||||
}
|
||||
}
|
||||
#include "tcss_dma.asl"
|
||||
}
|
||||
|
||||
/*
|
||||
* TCSS DMA1 device
|
||||
*/
|
||||
Device (TDM1)
|
||||
{
|
||||
Name (_ADR, 0x000D0003)
|
||||
Name (_DDN, "TBT DMA1 controller")
|
||||
Name (_STR, Unicode ("TBT DMA1 controller"))
|
||||
Name (DUID, 1) /* TBT DMA number */
|
||||
Name (DCPM, TCSS_DMA1)
|
||||
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
If (DME1 == 1) {
|
||||
Return (0x0F)
|
||||
} Else {
|
||||
Return (0x0)
|
||||
}
|
||||
}
|
||||
#include "tcss_dma.asl"
|
||||
}
|
||||
|
||||
/*
|
||||
* TCSS PCIE Root Port #00
|
||||
*/
|
||||
Device (TRP0)
|
||||
{
|
||||
Name (_ADR, 0x00070000)
|
||||
Name (TUID, 0) /* TBT PCIE RP Number 0 for RP00 */
|
||||
Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */
|
||||
Name (LMSL, 0) /* PCIE LTR max snoop Latency */
|
||||
Name (LNSL, 0) /* PCIE LTR max no snoop Latency */
|
||||
Name (DCPM, TCSS_TBT_PCIE0_RP0)
|
||||
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
If (VDID != 0xFFFFFFFF) {
|
||||
Return (0x0F)
|
||||
} Else {
|
||||
Return (0x0)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_INI)
|
||||
{
|
||||
LTEN = 0
|
||||
LMSL = 0x88C8
|
||||
LNSL = 0x88C8
|
||||
}
|
||||
#include "tcss_pcierp.asl"
|
||||
}
|
||||
|
||||
/*
|
||||
* TCSS PCIE Root Port #01
|
||||
*/
|
||||
Device (TRP1)
|
||||
{
|
||||
Name (_ADR, 0x00070001)
|
||||
Name (TUID, 1) /* TBT PCIE RP Number 1 for RP01 */
|
||||
Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */
|
||||
Name (LMSL, 0) /* PCIE LTR max snoop Latency */
|
||||
Name (LNSL, 0) /* PCIE LTR max no snoop Latency */
|
||||
Name (DCPM, TCSS_TBT_PCIE0_RP1)
|
||||
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
If (VDID != 0xFFFFFFFF) {
|
||||
Return (0x0F)
|
||||
} Else {
|
||||
Return (0x0)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_INI)
|
||||
{
|
||||
LTEN = 0
|
||||
LMSL = 0x88C8
|
||||
LNSL = 0x88C8
|
||||
}
|
||||
#include "tcss_pcierp.asl"
|
||||
}
|
||||
|
||||
/*
|
||||
* TCSS PCIE Root Port #02
|
||||
*/
|
||||
Device (TRP2)
|
||||
{
|
||||
Name (_ADR, 0x00070002)
|
||||
Name (TUID, 2) /* TBT PCIE RP Number 2 for RP02 */
|
||||
Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */
|
||||
Name (LMSL, 0) /* PCIE LTR max snoop Latency */
|
||||
Name (LNSL, 0) /* PCIE LTR max no snoop Latency */
|
||||
Name (DCPM, TCSS_TBT_PCIE0_RP2)
|
||||
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
If (VDID != 0xFFFFFFFF) {
|
||||
Return (0x0F)
|
||||
} Else {
|
||||
Return (0x0)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_INI)
|
||||
{
|
||||
LTEN = 0
|
||||
LMSL = 0x88C8
|
||||
LNSL = 0x88C8
|
||||
}
|
||||
#include "tcss_pcierp.asl"
|
||||
}
|
||||
|
||||
/*
|
||||
* TCSS PCIE Root Port #03
|
||||
*/
|
||||
Device (TRP3)
|
||||
{
|
||||
Name (_ADR, 0x00070003)
|
||||
Name (TUID, 3) /* TBT PCIE RP Number 3 for RP03 */
|
||||
Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */
|
||||
Name (LMSL, 0) /* PCIE LTR max snoop Latency */
|
||||
Name (LNSL, 0) /* PCIE LTR max no snoop Latency */
|
||||
Name (DCPM, TCSS_TBT_PCIE0_RP3)
|
||||
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
If (VDID != 0xFFFFFFFF) {
|
||||
Return (0x0F)
|
||||
} Else {
|
||||
Return (0x0)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_INI)
|
||||
{
|
||||
LTEN = 0
|
||||
LMSL = 0x88C8
|
||||
LNSL = 0x88C8
|
||||
}
|
||||
#include "tcss_pcierp.asl"
|
||||
}
|
||||
}
|
||||
108
src/soc/intel/pantherlake/acpi/tcss_dma.asl
Normal file
108
src/soc/intel/pantherlake/acpi/tcss_dma.asl
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
OperationRegion (DPME, SystemMemory, BASE(_ADR), 0x100)
|
||||
Field (DPME, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
VDID, 32,
|
||||
Offset(0x84), /* 0x84, DMA CFG PM CAP */
|
||||
PMST, 2, /* 1:0, PM_STATE */
|
||||
, 6,
|
||||
PMEE, 1, /* 8, PME_EN */
|
||||
, 6,
|
||||
PMES, 1, /* 15, PME_STATUS */
|
||||
Offset(0xc8), /* 0xC8, TBT NVM FW Revision */
|
||||
, 31,
|
||||
INFR, 1, /* TBT NVM FW Ready */
|
||||
Offset(0xec), /* 0xEC, TBT TO PCIE Register */
|
||||
TB2P, 32, /* TBT to PCIe */
|
||||
P2TB, 32, /* PCIe to TBT */
|
||||
Offset(0xfc), /* 0xFC, DMA RTD3 Force Power */
|
||||
DD3E, 1, /* 0:0 DMA RTD3 Enable */
|
||||
DFPE, 1, /* 1:1 DMA Force Power */
|
||||
Offset (0xff),
|
||||
DMAD, 8 /* 31:24 DMA Active Delay */
|
||||
}
|
||||
|
||||
Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
|
||||
|
||||
Method (_S0W, 0x0)
|
||||
{
|
||||
#if CONFIG(D3COLD_SUPPORT)
|
||||
Return (0x04)
|
||||
#else
|
||||
Return (0x03)
|
||||
#endif // D3COLD_SUPPORT
|
||||
}
|
||||
|
||||
/*
|
||||
* Get power resources that are dependent on this device for Operating System Power Management
|
||||
* to put the device in the D0 device state
|
||||
*/
|
||||
Method (_PR0)
|
||||
{
|
||||
#if CONFIG(D3COLD_SUPPORT)
|
||||
If (DUID == 0) {
|
||||
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
|
||||
} Else {
|
||||
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
|
||||
}
|
||||
#else
|
||||
If (DUID == 0) {
|
||||
Return (Package() { \_SB.PCI0.TBT0 })
|
||||
} Else {
|
||||
Return (Package() { \_SB.PCI0.TBT1 })
|
||||
}
|
||||
#endif // D3COLD_SUPPORT
|
||||
}
|
||||
|
||||
Method (_PR3)
|
||||
{
|
||||
#if CONFIG(D3COLD_SUPPORT)
|
||||
If (DUID == 0) {
|
||||
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
|
||||
} Else {
|
||||
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
|
||||
}
|
||||
#else
|
||||
If (DUID == 0) {
|
||||
Return (Package() { \_SB.PCI0.TBT0 })
|
||||
} Else {
|
||||
Return (Package() { \_SB.PCI0.TBT1 })
|
||||
}
|
||||
#endif // D3COLD_SUPPORT
|
||||
}
|
||||
|
||||
/*
|
||||
* RTD3 Exit Method to bring TBT controller out of RTD3 mode.
|
||||
*/
|
||||
Method (D3CX, 0, Serialized)
|
||||
{
|
||||
DD3E = 0x00 /* Disable DMA RTD3 */
|
||||
STAT = 0x01
|
||||
}
|
||||
|
||||
/*
|
||||
* RTD3 Entry method to enable TBT controller RTD3 mode.
|
||||
*/
|
||||
Method (D3CE, 0, Serialized)
|
||||
{
|
||||
DD3E = 0x01 /* Enable DMA RTD3 */
|
||||
STAT = 0x00
|
||||
}
|
||||
|
||||
/*
|
||||
* Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE
|
||||
* TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0.
|
||||
*/
|
||||
Name (SD3C, 0)
|
||||
|
||||
Method (_DSW, 3)
|
||||
{
|
||||
/* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */
|
||||
SD3C = Arg1
|
||||
}
|
||||
|
||||
Method (_PRW, 0)
|
||||
{
|
||||
Return (Package() { 0x65, 4 })
|
||||
}
|
||||
335
src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
Normal file
335
src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
Normal file
|
|
@ -0,0 +1,335 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
/*
|
||||
* TCSS PCIE RP Channel Configuration (CCFG) Config Space register offsets
|
||||
* MPC - Miscellaneous Port Configuration Register
|
||||
* RPPGEN - Root Port Power Gating Enable Register
|
||||
* SMSCS - SMI/SCI Status Register
|
||||
*/
|
||||
#define PXCS_OPREGION_SIZE 0xc00
|
||||
#define TCSS_CFG_MPC_FROM_CCFG 0xba8
|
||||
#define TCSS_CFG_SMSCS_FROM_CCFG 0xbac
|
||||
#define TCSS_CFG_RPPGEN_FROM_CCFG 0xbb2
|
||||
|
||||
OperationRegion (PXCS, SystemMemory, BASE(_ADR), PXCS_OPREGION_SIZE)
|
||||
Field (PXCS, AnyAcc, NoLock, Preserve)
|
||||
{
|
||||
VDID, 32,
|
||||
Offset(0x50), /* LCTL - Link Control Register */
|
||||
L0SE, 1, /* 0, L0s Entry Enabled */
|
||||
, 3,
|
||||
LDIS, 1, /* 1, Link Disable */
|
||||
, 4,
|
||||
Offset(0x52), /* LSTS - Link Status Register */
|
||||
, 13,
|
||||
LASX, 1, /* 0, Link Active Status */
|
||||
Offset(0x5a), /* SLSTS[7:0] - Slot Status Register */
|
||||
ABPX, 1, /* 0, Attention Button Pressed */
|
||||
, 2,
|
||||
PDCX, 1, /* 3, Presence Detect Changed */
|
||||
, 2,
|
||||
PDSX, 1, /* 6, Presence Detect State */
|
||||
, 1,
|
||||
DLSC, 1, /* 8, Data Link Layer State Changed */
|
||||
Offset(0x60), /* RSTS - Root Status Register */
|
||||
Offset(0x62),
|
||||
PSPX, 1, /* 16, PME Status */
|
||||
Offset (0x68),
|
||||
, 10,
|
||||
LNRE, 1, /* LTR Mechanism Enable */
|
||||
Offset(0xA4),
|
||||
D3HT, 2, /* Power State */
|
||||
Offset (0x404),
|
||||
LSOE, 1,
|
||||
LNSE, 1,
|
||||
Offset(0x420), /* 0x420, PCIEPMECTL (PCIe PM Extension Control) */
|
||||
, 30,
|
||||
DPGE, 1, /* PCIEPMECTL[30]: Disabled, Detect and L23_Rdy State PHY Lane */
|
||||
/* Power Gating Enable (DLSULPPGE) */
|
||||
Offset(0x5bc), /* 0x5bc, PCIE ADVMCTRL */
|
||||
, 3,
|
||||
RPER, 1, /* RTD3PERST[3] */
|
||||
RPFE, 1, /* RTD3PFETDIS[4] */
|
||||
Offset(TCSS_CFG_MPC_FROM_CCFG), /* 0xba8, MPC - Miscellaneous Port Configuration Register */
|
||||
, 30,
|
||||
HPEX, 1, /* 30, Hot Plug SCI Enable */
|
||||
PMEX, 1, /* 31, Power Management SCI Enable */
|
||||
Offset(TCSS_CFG_RPPGEN_FROM_CCFG), /* 0xbb2, RPPGEN - Root Port Power Gating Enable */
|
||||
, 2,
|
||||
L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
|
||||
L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
|
||||
}
|
||||
|
||||
Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
|
||||
{
|
||||
Offset(TCSS_CFG_SMSCS_FROM_CCFG), /* 0xbac, SMSCS - SMI/SCI Status Register */
|
||||
, 30,
|
||||
HPSX, 1, /* 30, Hot Plug SCI Status */
|
||||
PMSX, 1 /* 31, Power Management SCI Status */
|
||||
}
|
||||
|
||||
/*
|
||||
* _DSM Device Specific Method
|
||||
*
|
||||
* Arg0: UUID Unique function identifier
|
||||
* Arg1: Integer Revision Level
|
||||
* Arg2: Integer Function Index (0 = Return Supported Functions)
|
||||
* Arg3: Package Parameters
|
||||
*/
|
||||
Method (_DSM, 4, Serialized)
|
||||
{
|
||||
Return (Buffer() { 0x00 })
|
||||
}
|
||||
|
||||
/*
|
||||
* A bitmask of functions support
|
||||
*/
|
||||
Name(OPTS, Buffer(2) {0, 0})
|
||||
|
||||
Device (PXSX)
|
||||
{
|
||||
Name (_ADR, 0x00000000)
|
||||
|
||||
/*
|
||||
* _DSM Device Specific Method
|
||||
*
|
||||
* Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
|
||||
* Arg1: Revision ID: 3
|
||||
* Arg2: Function index: 0, 9
|
||||
* Arg3: Empty package
|
||||
*/
|
||||
Method (_DSM, 4, Serialized)
|
||||
{
|
||||
If (Arg0 == ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) {
|
||||
If (Arg1 >= 3) {
|
||||
If (Arg2 == 0) {
|
||||
/*
|
||||
* Function index: 0
|
||||
* Standard query - A bitmask of functions supported
|
||||
*/
|
||||
CreateBitField(OPTS, 9, FUN9)
|
||||
FUN9 = 1
|
||||
Return (OPTS)
|
||||
} ElseIf (Arg2 == 9) {
|
||||
/*
|
||||
* Function index: 9
|
||||
* Specifying device readiness durations
|
||||
*/
|
||||
Return (Package() { FW_RESET_TIME, FW_DL_UP_TIME,
|
||||
FW_FLR_RESET_TIME, FW_D3HOT_TO_D0_TIME,
|
||||
FW_VF_ENABLE_TIME })
|
||||
}
|
||||
}
|
||||
}
|
||||
Return (Buffer() { 0x0 })
|
||||
}
|
||||
|
||||
Method (_PRW, 0)
|
||||
{
|
||||
Return (Package() { 0x76, 4 })
|
||||
}
|
||||
}
|
||||
|
||||
Method (_DSW, 3)
|
||||
{
|
||||
/* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */
|
||||
If ((TUID == 0) || (TUID == 1)) {
|
||||
\_SB.PCI0.TDM0.SD3C = Arg1
|
||||
} Else {
|
||||
\_SB.PCI0.TDM1.SD3C = Arg1
|
||||
}
|
||||
|
||||
C2PM (Arg0, Arg1, Arg2, DCPM)
|
||||
}
|
||||
|
||||
Method (_PRW, 0)
|
||||
{
|
||||
Return (Package() { 0x76, 4 })
|
||||
}
|
||||
|
||||
/*
|
||||
* Sub-Method of _L61 Hot-Plug event
|
||||
* _L61 event handler should invoke this method to support HotPlug wake event from TBT RP.
|
||||
*/
|
||||
Method (HPEV, 0, Serialized)
|
||||
{
|
||||
If ((VDID != 0xFFFFFFFF) && HPSX) {
|
||||
If ((PDCX == 1) && (DLSC == 1)) {
|
||||
/* Clear all status bits first. */
|
||||
PDCX = 1
|
||||
HPSX = 1
|
||||
|
||||
/* Perform proper notification to the OS. */
|
||||
Notify (^, 0)
|
||||
} Else {
|
||||
/* False event. Clear Hot-Plug Status, then exit. */
|
||||
HPSX = 1
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Power Management routine for D3
|
||||
*/
|
||||
Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
|
||||
|
||||
/*
|
||||
* RTD3 Exit Method to bring TBT controller out of RTD3 mode.
|
||||
*/
|
||||
Method (D3CX, 0, Serialized)
|
||||
{
|
||||
If (STAT == 0x1) {
|
||||
Return
|
||||
}
|
||||
|
||||
RPFE = 0 /* Set RTD3PFETDIS = 0 */
|
||||
RPER = 0 /* Set RTD3PERST = 0 */
|
||||
L23R = 1 /* Set L23r2dt = 1 */
|
||||
|
||||
/*
|
||||
* Poll for L23r2dt == 0. Wait for transition to Detect.
|
||||
*/
|
||||
Local0 = 0
|
||||
Local1 = L23R
|
||||
While (Local1) {
|
||||
If (Local0 > 20) {
|
||||
Break
|
||||
}
|
||||
Sleep(5)
|
||||
Local0++
|
||||
Local1 = L23R
|
||||
}
|
||||
STAT = 0x1
|
||||
}
|
||||
|
||||
/*
|
||||
* RTD3 Entry method to enable TBT controller RTD3 mode.
|
||||
*/
|
||||
Method (D3CE, 0, Serialized)
|
||||
{
|
||||
If (STAT == 0x0) {
|
||||
Return
|
||||
}
|
||||
|
||||
If ((LNSE == 1) || (LSOE == 1)) {
|
||||
If ((LASX == 1) && (LNRE == 0)) {
|
||||
LNRE = 1
|
||||
Sleep(1)
|
||||
LNRE = 0
|
||||
}
|
||||
}
|
||||
|
||||
L23E = 1 /* Set L23er = 1 */
|
||||
|
||||
/* Poll until L23er == 0 */
|
||||
Local0 = 0
|
||||
Local1 = L23E
|
||||
While (Local1) {
|
||||
If (Local0 > 20) {
|
||||
Break
|
||||
}
|
||||
Sleep(5)
|
||||
Local0++
|
||||
Local1 = L23E
|
||||
}
|
||||
|
||||
STAT = 0 /* D3Cold */
|
||||
RPFE = 1 /* Set RTD3PFETDIS = 1 */
|
||||
RPER = 1 /* Set RTD3PERST = 1 */
|
||||
}
|
||||
|
||||
Method (_PS0, 0, Serialized)
|
||||
{
|
||||
HPEV () /* Check and handle Hot Plug SCI status. */
|
||||
If (HPEX == 1) {
|
||||
HPEX = 0 /* Disable Hot Plug SCI */
|
||||
}
|
||||
HPME () /* Check and handle PME SCI status */
|
||||
If (PMEX == 1) {
|
||||
PMEX = 0 /* Disable Power Management SCI */
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PS3, 0, Serialized)
|
||||
{
|
||||
/* Check it is hotplug SCI or not, then clear PDC accordingly */
|
||||
If (PDCX == 1) {
|
||||
If (DLSC == 0) {
|
||||
/* Clear PDC since it is not a hotplug. */
|
||||
PDCX = 1
|
||||
}
|
||||
}
|
||||
|
||||
If (HPEX == 0) {
|
||||
HPEX = 1 /* Enable Hot Plug SCI. */
|
||||
HPEV () /* Check and handle Hot Plug SCI status. */
|
||||
}
|
||||
If (PMEX == 0) {
|
||||
PMEX = 1 /* Enable Power Management SCI. */
|
||||
HPME () /* Check and handle PME SCI status. */
|
||||
}
|
||||
}
|
||||
|
||||
Method (_S0W, 0x0, NotSerialized)
|
||||
{
|
||||
#if CONFIG(D3COLD_SUPPORT)
|
||||
Return (0x4)
|
||||
#else
|
||||
Return (0x3)
|
||||
#endif // D3COLD_SUPPORT
|
||||
}
|
||||
|
||||
Method (_PR0)
|
||||
{
|
||||
#if CONFIG(D3COLD_SUPPORT)
|
||||
If ((TUID == 0) || (TUID == 1)) {
|
||||
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
|
||||
} Else {
|
||||
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
|
||||
}
|
||||
#else
|
||||
If ((TUID == 0) || (TUID == 1)) {
|
||||
Return (Package() { \_SB.PCI0.TBT0 })
|
||||
} Else {
|
||||
Return (Package() { \_SB.PCI0.TBT1 })
|
||||
}
|
||||
#endif // D3COLD_SUPPORT
|
||||
}
|
||||
|
||||
Method (_PR3)
|
||||
{
|
||||
#if CONFIG(D3COLD_SUPPORT)
|
||||
If ((TUID == 0) || (TUID == 1)) {
|
||||
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
|
||||
} Else {
|
||||
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
|
||||
}
|
||||
#else
|
||||
If ((TUID == 0) || (TUID == 1)) {
|
||||
Return (Package() { \_SB.PCI0.TBT0 })
|
||||
} Else {
|
||||
Return (Package() { \_SB.PCI0.TBT1 })
|
||||
}
|
||||
#endif // D3COLD_SUPPORT
|
||||
}
|
||||
|
||||
/*
|
||||
* PCI_EXP_STS Handler for PCIE Root Port
|
||||
*/
|
||||
Method (HPME, 0, Serialized)
|
||||
{
|
||||
If ((VDID != 0xFFFFFFFF) && (PMSX == 1)) { /* if port exists and PME SCI Status set */
|
||||
/*
|
||||
* Notify child device; this will cause its driver to clear PME_Status from
|
||||
* device.
|
||||
*/
|
||||
Notify (PXSX, 0x2)
|
||||
PMSX = 1 /* clear rootport's PME SCI status */
|
||||
/*
|
||||
* Consume one pending PME notification to prevent it from blocking the queue.
|
||||
*/
|
||||
PSPX = 1
|
||||
Return (0x01)
|
||||
}
|
||||
Return (0x00)
|
||||
}
|
||||
188
src/soc/intel/pantherlake/acpi/tcss_xhci.asl
Normal file
188
src/soc/intel/pantherlake/acpi/tcss_xhci.asl
Normal file
|
|
@ -0,0 +1,188 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
OperationRegion (XPRT, SystemMemory, BASE(_ADR), 0x100)
|
||||
Field (XPRT, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
VDID, 32,
|
||||
Offset(0x74), /* 0x74, XHCI CFG Power Control And Status */
|
||||
D0D3, 2, /* 0x74 BIT[1:0] */
|
||||
, 6,
|
||||
PMEE, 1, /* PME Enable */
|
||||
, 6,
|
||||
PMES, 1, /* PME Status */
|
||||
}
|
||||
|
||||
Method (_PS0, 0, Serialized)
|
||||
{
|
||||
If (\_SB.PCI0.TXHC.PMEE == 1) {
|
||||
/* Clear PME_EN of CPU xHCI */
|
||||
\_SB.PCI0.TXHC.PMEE = 0
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PS3, 0, Serialized)
|
||||
{
|
||||
If (\_SB.PCI0.TXHC.PMEE == 0) {
|
||||
/* Set PME_EN of CPU xHCI */
|
||||
\_SB.PCI0.TXHC.PMEE = 1
|
||||
}
|
||||
}
|
||||
|
||||
Method (_S0W, 0x0, NotSerialized)
|
||||
{
|
||||
#if CONFIG(D3COLD_SUPPORT)
|
||||
Return (0x4)
|
||||
#else
|
||||
Return (0x3)
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE
|
||||
* TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0.
|
||||
*/
|
||||
Name (SD3C, 0)
|
||||
|
||||
#if CONFIG(D3COLD_SUPPORT)
|
||||
Method (_PR0)
|
||||
{
|
||||
Return (Package () { \_SB.PCI0.D3C })
|
||||
}
|
||||
|
||||
Method (_PR3)
|
||||
{
|
||||
Return (Package () { \_SB.PCI0.D3C })
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* XHCI controller _DSM method
|
||||
*/
|
||||
Method (_DSM, 4, serialized)
|
||||
{
|
||||
Return (Buffer() { 0 })
|
||||
}
|
||||
|
||||
/*
|
||||
* _SXD and _SXW methods
|
||||
*/
|
||||
Method (_S3D, 0, NotSerialized)
|
||||
{
|
||||
Return (3)
|
||||
}
|
||||
|
||||
Method (_S4D, 0, NotSerialized)
|
||||
{
|
||||
Return (3)
|
||||
}
|
||||
|
||||
Method (_S3W, 0, NotSerialized)
|
||||
{
|
||||
Return (3)
|
||||
}
|
||||
|
||||
Method (_S4W, 0, NotSerialized)
|
||||
{
|
||||
Return (3)
|
||||
}
|
||||
|
||||
/*
|
||||
* Power resource for wake
|
||||
*/
|
||||
Method (_PRW, 0)
|
||||
{
|
||||
Return (Package() { 0x65, 4 })
|
||||
}
|
||||
|
||||
/*
|
||||
* Device sleep wake
|
||||
*/
|
||||
Method (_DSW, 3)
|
||||
{
|
||||
C2PM (Arg0, Arg1, Arg2, DCPM)
|
||||
/* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */
|
||||
SD3C = Arg1
|
||||
}
|
||||
|
||||
/*
|
||||
* xHCI Root Hub Device
|
||||
*/
|
||||
Device (RHUB)
|
||||
{
|
||||
Name (_ADR, 0)
|
||||
|
||||
/* High Speed Ports */
|
||||
Device (HS01)
|
||||
{
|
||||
Name (_ADR, 0x01)
|
||||
}
|
||||
|
||||
/* Super Speed Ports */
|
||||
Device (SS01)
|
||||
{
|
||||
Name (_ADR, 0x02)
|
||||
Method (_DSD, 0, NotSerialized)
|
||||
{
|
||||
Return( Package ()
|
||||
{
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package ()
|
||||
{
|
||||
Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 },
|
||||
Package (2) { "usb4-port-number", 0 }
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
Device (SS02)
|
||||
{
|
||||
Name (_ADR, 0x03)
|
||||
Method (_DSD, 0, NotSerialized)
|
||||
{
|
||||
Return( Package ()
|
||||
{
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package ()
|
||||
{
|
||||
Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 },
|
||||
Package (2) { "usb4-port-number", 1 }
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
Device (SS03)
|
||||
{
|
||||
Name (_ADR, 0x04)
|
||||
Method (_DSD, 0, NotSerialized)
|
||||
{
|
||||
Return( Package ()
|
||||
{
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package ()
|
||||
{
|
||||
Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 },
|
||||
Package (2) { "usb4-port-number", 0 }
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
Device (SS04)
|
||||
{
|
||||
Name (_ADR, 0x05)
|
||||
Method (_DSD, 0, NotSerialized)
|
||||
{
|
||||
Return( Package ()
|
||||
{
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package ()
|
||||
{
|
||||
Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 },
|
||||
Package (2) { "usb4-port-number", 1 }
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
}
|
||||
46
src/soc/intel/pantherlake/acpi/xhci.asl
Normal file
46
src/soc/intel/pantherlake/acpi/xhci.asl
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/gpe.h>
|
||||
|
||||
/* XHCI Controller 0:14.0 */
|
||||
|
||||
Device (XHCI)
|
||||
{
|
||||
Name (_ADR, 0x00140000)
|
||||
|
||||
Name (_PRW, Package () { GPE0_PME_B0, 3 })
|
||||
|
||||
Name (_S3D, 3) /* D3 supported in S3 */
|
||||
Name (_S0W, 3) /* D3 can wake device in S0 */
|
||||
Name (_S3W, 3) /* D3 can wake system from S3 */
|
||||
|
||||
Method (_PS0, 0, Serialized)
|
||||
{
|
||||
/* Disable Clock Gating */
|
||||
^^PCRA (PID_XHCI, 0x0, ~(1 << 3))
|
||||
}
|
||||
|
||||
Method (_PS3, 0, Serialized)
|
||||
{
|
||||
/* Enable Clock Gating */
|
||||
^^PCRO (PID_XHCI, 0x0, 1 << 3)
|
||||
}
|
||||
|
||||
Device (RHUB)
|
||||
{
|
||||
Name (_ADR, 0)
|
||||
|
||||
/* USB2 */
|
||||
Device (HS01) { Name (_ADR, 1) }
|
||||
Device (HS02) { Name (_ADR, 2) }
|
||||
Device (HS03) { Name (_ADR, 3) }
|
||||
Device (HS04) { Name (_ADR, 4) }
|
||||
Device (HS05) { Name (_ADR, 5) }
|
||||
Device (HS06) { Name (_ADR, 6) }
|
||||
Device (HS07) { Name (_ADR, 7) }
|
||||
Device (HS08) { Name (_ADR, 8) }
|
||||
/* USB3 */
|
||||
Device (SS01) { Name (_ADR, 11) }
|
||||
Device (SS02) { Name (_ADR, 12) }
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue