soc/intel/xeon_sp/gnr: Support full IIO UPD configurations
Change-Id: Iebfadffd2da83992af983b8c0dfe2706f81eb728 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84317 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shuo Liu
Lean Sheng Tan
parent
4725e57a95
commit
475565e9cc
2 changed files with 76 additions and 31 deletions
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@ -44,31 +44,39 @@ struct iio_port_config {
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uint8_t vpp_mux_address; // SMBUS address of MUX used to access VPP
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uint8_t vpp_mux_channel; // Channel of the MUX used to access VPP
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uint8_t slot_eip:1; // Electromechanical Interlock Present -
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uint8_t npem_address; // SMBUS address of IO expander which provides NPEM
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uint8_t npem_bank; // Port or bank on IoExpander which provides NPEM
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uint8_t npem_mux_address; // SMBUS address of MUX used to access NPEM
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uint8_t npem_mux_channel; // Channel of the MUX used to access NPEM
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uint8_t slot_eip; // Electromechanical Interlock Present -
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// Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
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uint8_t slot_hps:1; // Hot Plug surprise supported -
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uint8_t slot_hps; // Hot Plug surprise supported -
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// Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
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uint8_t slot_pind:1; // Power Indicator Present -
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uint8_t slot_pind; // Power Indicator Present -
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// Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
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uint8_t slot_aind:1; // Attention Inductor Present -
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uint8_t slot_aind; // Attention Inductor Present -
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// Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
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uint8_t slot_pctl:1; // Power Controller Present -
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uint8_t slot_pctl; // Power Controller Present -
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// Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
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uint8_t slot_abtn:1; // Attention Button Present -
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uint8_t slot_abtn; // Attention Button Present -
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// Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
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uint8_t slot_rsvd:2; // Reserved
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uint8_t vpp_enabled:1; // If VPP is supported on given port
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uint8_t vpp_exp_type:1; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE
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uint8_t vpp_enabled; // If VPP is supported on given port
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uint8_t vpp_exp_type; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE
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// for values definitions)
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uint8_t npem_supported; // If NPEM is supported on given port
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uint8_t slot_implemented:1;
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uint8_t reserved:4;
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uint8_t slot_implemented;
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uint8_t retimer_1_present;
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uint8_t retimer_2_present;
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uint8_t common_clock;
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uint8_t sris;
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uint16_t hot_plug:1; // If hotplug is supported on slot connected to this port
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uint16_t mrl_sensor_present:1; // If MRL is present on slot connected to this port
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uint16_t slot_power_limit_scale:2; // Slot Power Scale for slot connected to this port
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uint16_t slot_power_limit_value:12; // Slot Power Value for slot connected to this port
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uint16_t hot_plug; // If hotplug is supported on slot connected to this port
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uint16_t mrl_sensor_present; // If MRL is present on slot connected to this port
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uint16_t slot_power_limit_scale; // Slot Power Scale for slot connected to this port
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uint16_t slot_power_limit_value; // Slot Power Value for slot connected to this port
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uint16_t physical_slot_number; // Slot number for slot connected to this port
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};
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@ -77,8 +85,8 @@ struct iio_pe_config {
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uint8_t socket;
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IIO_PACKAGE_PE pe;
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IIO_BIFURCATION bifurcation;
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uint8_t cxl_support:1;
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uint8_t reserved:7;
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uint8_t cxl_support;
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uint8_t reserved;
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struct iio_port_config port_config[MAX_IIO_PORTS_PER_STACK];
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};
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@ -102,11 +110,12 @@ struct iio_pe_config {
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.reserved = 0,\
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.port_config =
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/* TODO: to update rsv1 - rsv5 after SoC launch */
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#define _IIO_PORT_CFG_STRUCT(vppen, vppex, vaddr, vport, vmuxa, vmuxc,\
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slteip, slthps, sltpind, sltaind, sltpctl, sltabtn, hotp, mrlsp,\
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sltimpl, sltpls, sltplv, psn,\
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rsv1, rsv2, rsv3, rsv4, rsv5) {\
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slteip, slthps, sltpind, sltaind, sltpctl, sltabtn,\
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sltimpl, hotp, mrlsp, sltpls, sltplv, psn,\
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retimer1, retimer2, comclk, dsris,\
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npmspt, npaddr, npb, npma, npmc\
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) {\
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.vpp_enabled = (vppen),\
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.vpp_exp_type = (vppex),\
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.vpp_address = (vaddr),\
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@ -119,32 +128,57 @@ struct iio_pe_config {
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.slot_aind = (sltaind),\
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.slot_pctl = (sltpctl),\
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.slot_abtn = (sltabtn),\
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.slot_rsvd = 0,\
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.slot_implemented = (sltimpl),\
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.reserved = 0,\
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.retimer_1_present = (retimer1),\
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.retimer_2_present = (retimer2),\
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.common_clock = (comclk),\
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.sris = (dsris),\
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.hot_plug = (hotp),\
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.mrl_sensor_present = (mrlsp),\
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.slot_power_limit_scale = (sltpls),\
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.slot_power_limit_value = (sltplv),\
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.physical_slot_number = (psn)\
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.physical_slot_number = (psn),\
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.npem_supported = (npmspt),\
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.npem_address = (npaddr),\
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.npem_bank = (npb),\
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.npem_mux_address = (npma),\
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.npem_mux_channel = (npmc),\
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}
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#define _IIO_PORT_CFG_STRUCT_DISABLED \
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_IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0)
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_IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
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0x0, 0x0, 0x0, 0x0,\
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0x0, 0x0, 0x0, 0x0, 0x0)
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#define _IIO_PORT_CFG_STRUCT_X8 _IIO_PORT_CFG_STRUCT
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#define _IIO_PORT_CFG_STRUCT_X4 _IIO_PORT_CFG_STRUCT
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#define _IIO_PORT_CFG_STRUCT_X2 _IIO_PORT_CFG_STRUCT
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#define _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn)\
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_IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
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0x0, 0x0, 0x0, 0x1, sltpls, sltplv, psn, 0x0, 0x0, 0x0, 0x0, 0x0)
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_IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0,\
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0x1, 0x0, 0x0, sltpls, sltplv, psn,\
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0x0, 0x0, 0x1, 0x0,\
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0x0, 0x0, 0x0, 0x0, 0x0)
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#define _IIO_PORT_CFG_STRUCT_BASIC_X8 _IIO_PORT_CFG_STRUCT_BASIC
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#define _IIO_PORT_CFG_STRUCT_BASIC_X4 _IIO_PORT_CFG_STRUCT_BASIC
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#define _IIO_PORT_CFG_STRUCT_BASIC_X2 _IIO_PORT_CFG_STRUCT_BASIC
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#define _IIO_PE_CFG_DISABLED(socket, pe) {\
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_IIO_PE_CFG_STRUCT(socket, pe, IIO_BIFURCATE_AUTO, PE_TYPE_PCIE) {\
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_IIO_PORT_CFG_STRUCT_DISABLED,\
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_IIO_PORT_CFG_STRUCT_DISABLED,\
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_IIO_PORT_CFG_STRUCT_DISABLED,\
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_IIO_PORT_CFG_STRUCT_DISABLED,\
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_IIO_PORT_CFG_STRUCT_DISABLED,\
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_IIO_PORT_CFG_STRUCT_DISABLED,\
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_IIO_PORT_CFG_STRUCT_DISABLED,\
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_IIO_PORT_CFG_STRUCT_DISABLED,\
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}}
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void soc_config_iio_pe_ports(FSPM_UPD *mupd, const struct iio_pe_config *config_table,
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unsigned int num_entries);
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@ -36,11 +36,21 @@ void soc_config_iio_pe_ports(FSPM_UPD *mupd, const struct iio_pe_config *config_
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upd_pe_config->Bifurcation = board_pe_config->bifurcation;
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upd_pe_config->CxlSupportInUba = board_pe_config->cxl_support;
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upd_port_config->VppEnabled = board_port_config->vpp_enabled;
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upd_port_config->VppExpType = board_port_config->vpp_exp_type;
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upd_port_config->Vpp.Address = board_port_config->vpp_address;
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upd_port_config->Vpp.Port = board_port_config->vpp_port;
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upd_port_config->Vpp.MuxAddress = board_port_config->vpp_mux_address;
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upd_port_config->Vpp.MuxChannel = board_port_config->vpp_mux_channel;
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upd_port_config->NpemSupported = board_port_config->npem_supported;
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upd_port_config->Npem.Address = board_port_config->npem_address;
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upd_port_config->Npem.Bank = board_port_config->npem_bank;
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upd_port_config->Npem.MuxAddress = board_port_config->npem_mux_address;
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upd_port_config->Npem.MuxChannel = board_port_config->npem_mux_channel;
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upd_port_config->Slot.Eip = board_port_config->slot_eip;
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upd_port_config->Slot.HotPlugSurprise = board_port_config->slot_hps;
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upd_port_config->Slot.PowerInd = board_port_config->slot_pind;
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@ -48,15 +58,16 @@ void soc_config_iio_pe_ports(FSPM_UPD *mupd, const struct iio_pe_config *config_
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upd_port_config->Slot.PowerCtrl = board_port_config->slot_pctl;
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upd_port_config->Slot.AttentionBtn = board_port_config->slot_abtn;
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upd_port_config->VppEnabled = board_port_config->vpp_enabled;
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upd_port_config->VppExpType = board_port_config->vpp_exp_type;
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upd_port_config->SlotImplemented = board_port_config->slot_implemented;
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upd_port_config->HotPlug = board_port_config->hot_plug;
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upd_port_config->MrlSensorPresent = board_port_config->mrl_sensor_present;
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upd_port_config->SlotPowerLimitScale = board_port_config->slot_power_limit_scale;
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upd_port_config->SlotPowerLimitValue = board_port_config->slot_power_limit_value;
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upd_port_config->PhysicalSlotNumber = board_port_config->physical_slot_number;
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upd_port_config->Retimer1Present = board_port_config->retimer_1_present;
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upd_port_config->Retimer2Present = board_port_config->retimer_2_present;
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upd_port_config->CommonClock = board_port_config->common_clock;
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upd_port_config->SRIS = board_port_config->sris;
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}
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}
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