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mb/google/brox/jubilant: Update cpu power limit settings

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1)Modify jubilant cpu power limit setting depend on the brox
  baseboad settgins,refer to CL:
  https://review.coreboot.org/c/coreboot/+/83752

2)Update PL1,PL2, and PL4 value from jubilant thermal design
   PL1 = 15W
   PL2 = 41W
   PL4 = 87W

BUG=b:364441688
BRANCH=None
TEST=Able to successfully boot on jubilant photo SKU1 and SKU2
     boards with AC w/o battery.
     Test on AC 65W and 45W w/o battery,and check the PL values.

Change-Id: I9a143d9faaa6c57b0d314c0ff6c0e55f556d7216
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
This commit is contained in:
Ren Kuo 2024-09-11 13:49:29 +08:00 • committed by Felix Held
commit 19788920cb
2 changed files with 16 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/mainboard/google/brox/variants/jubilant/overridetree.cb
View file

@ -75,6 +75,12 @@ chip soc/intel/alderlake
},
}"
register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 41,
.tdp_pl4 = 87,
}"
device domain 0 on
device ref dtt on
chip drivers/intel/dptf

31
src/mainboard/google/brox/variants/jubilant/ramstage.c
View file

@ -15,33 +15,23 @@ const struct cpu_power_limits performance_efficient_limits[] = {
{
.mchid = PCI_DID_INTEL_RPL_P_ID_3,
.cpu_tdp = 15,
.pl1_min_power = 6000,
.pl1_max_power = 15000,
.pl2_min_power = 55000,
.pl2_max_power = 55000,
.pl4_power = 114000
.pl1_min_power = 15000,
.pl1_max_power = 18000,
.pl2_min_power = 41000,
.pl2_max_power = 41000,
.pl4_power = 87000
},
{
.mchid = PCI_DID_INTEL_RPL_P_ID_4,
.cpu_tdp = 15,
.pl1_min_power = 6000,
.pl1_max_power = 15000,
.pl2_min_power = 55000,
.pl2_max_power = 55000,
.pl4_power = 114000
.pl1_min_power = 15000,
.pl1_max_power = 18000,
.pl2_min_power = 41000,
.pl2_max_power = 41000,
.pl4_power = 87000
},
};
const struct system_power_limits sys_limits[] = {
/* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
{ PCI_DID_INTEL_RPL_P_ID_3, 15, 60 },
{ PCI_DID_INTEL_RPL_P_ID_4, 15, 60 },
};
const struct psys_config psys_config = {
.efficiency = 86,
};
void __weak variant_devtree_update(void)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
@ -50,5 +40,4 @@ void __weak variant_devtree_update(void)
size_t limits_size = ARRAY_SIZE(performance_efficient_limits);
variant_update_power_limits(limits, limits_size);
variant_update_psys_power_limits(limits, sys_limits, limits_size, &psys_config);
}