mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl5}: Enable real-time tuning in FSP

The real-time feature should also be activated for all mc_ehl
mainboards, as it has already been done for mainboard mc_ehl1. It
improves performance in the real-time environment for these mainboards.

Change-Id: I04859b2f32bc11344b0620925f2414e7a6df625e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84391
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb

@@ -133,6 +133,9 @@ chip soc/intel/elkhartlake
 	# Disable L1 prefetcher for real-time demands
 	register "L1_prefetcher_disable" = "true"
 
+	# Enable real-time tuning
+	register "realtime_tuning_enable" = "true"
+
 	device domain 0 on
 		device pci 00.0 on	end # Host Bridge
 		device pci 02.0 on	end # Integrated Graphics Device

src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb

@@ -135,6 +135,9 @@ chip soc/intel/elkhartlake
 	# Disable L1 prefetcher for real-time demands
 	register "L1_prefetcher_disable" = "true"
 
+	# Enable real-time tuning
+	register "realtime_tuning_enable" = "true"
+
 	device domain 0 on
 		device pci 00.0 on	end # Host Bridge
 		device pci 02.0 on	end # Integrated Graphics Device

src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb

@@ -133,6 +133,9 @@ chip soc/intel/elkhartlake
 	# Disable L1 prefetcher for real-time demands
 	register "L1_prefetcher_disable" = "true"
 
+	# Enable real-time tuning
+	register "realtime_tuning_enable" = "true"
+
 	device domain 0 on
 		device pci 00.0 on	end # Host Bridge
 		device pci 02.0 on	end # Integrated Graphics Device