erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"

Browse source 
This reverts commit 88a496a9c8.

This workaround is not valid with the latest Intel PRQ silicon,
so I'm dropping it now. Additionally, able to boot to ChromeOS without
any hang, and I also ran an S0ix cycle without any failures.

BUG=b:244082753
TEST=Able to boot google/rex0 to CrOS.

Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84368
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2024-09-15 10:50:19 +00:00
commit b9a09786bc
1 changed files with 1 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

8
src/soc/intel/meteorlake/acpi/tcss.asl
View file

@ -602,13 +602,7 @@ Scope (\_SB.PCI0)
}
/* Request IOM for D3 cold entry sequence. */
/*
* FIXME: Remove this workaround after resolving b/244082753
*
* Document #742990: TCCold exit flow may not complete when processor at package
* C0. The implication is that the system may hang.
*/
// TD3C = 1
TD3C = 1
}
PowerResource (D3C, 5, 0)