Rename `fill_lb_framebuffer` to `get_lb_framebuffer` to better
reflect that it returns framebuffer information.
The new `get_lb_framebuffer` returns a constant pointer to the
framebuffer structure instead of filling a provided structure.
This simplifies the API and avoids an unnecessary memory copy.
The file `edid_fill_fb.c` is renamed to `framebuffer_info.c`
to better match the function it now contains.
Call sites in `coreboot_table.c` and `render_bmp.c` are
updated to use the new API.
TEST=emerge-tanjiro coreboot; check the FW logo is correctly drawn.
BUG=b:319511268
Change-Id: I8d7b20a0524b6bc9fff9e6461fa0c253345df790
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90725
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Increased MHBR field width in ACPI northbridge.asl from 17 to 27 bits,
allowing MCHBAR to be set above 4GB (up to 42 bits).
Reference: Section 10.3 in 850519
BUG=none
TEST=boot to OS with ACPI debug enabled and check GMHB log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I885ff64598367ddadcec05926af3556024b61250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90729
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
AMD systems support 8-bit IOAPIC IDs. Some silicon initialization code
modules, like OpenSIL, may allocate an 8-bit ID by default. To respect
that configuration or set ID properly in coreboot, whole 8-bit ID field
has to be cleared and set.
Add new IOAPIC_8BIT_ID Kconfig option to allow setting 8-bit long IOAPIC
IDs.
TEST=Set IOAPIC IDs starting with 240 on Gigabyte MZ33-AR1.
Change-Id: Ie85b2272b0bc64a95d76c5677816941f1334901d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Introduce a centralized helper function, dt_add_reserved_memory_region,
to simplify the creation of sub-nodes under /reserved-memory.
Currently, various features (such as pKVM, ramoops, and platform-
specific firmware reservations) manually handle the creation of
reserved memory nodes. This involves repetitive logic for:
- Navigating or creating the /reserved-memory parent path.
- Calculating cell sizes for 'reg' properties.
- Manually adding 'no-map' or 'compatible' properties.
This helper abstracts those steps into a single call, reducing
boilerplate and the risk of cell-size mismatches across the codebase.
The function handles:
- Node creation if the path doesn't exist.
- Optional 'compatible' string assignment.
- Automatic 'reg' property generation using appropriate address/size
cells.
- Optional 'no-map' property assignment via a boolean flag.
Change-Id: Ie58f5fdcfd1863b41c177b63ed9fc25d6d220e3a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90713
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Based on the WiFi firmware configuration to add function for
getting WiFi SAR cbfs filename.
BUG=b:460231264
TEST=Build and check the system could boot to OS, and check the SAR table could work fine.
Change-Id: Ieec65debdc9f506e779352fcf8e54daa9296c0f7
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90376
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ICH SPI controller fails when a single transfer spans a 4KiB
boundary. Limit data_length in spi_ctrlr_xfer() to stay within the
current 4KiB page when with_address is true, avoiding the hardware
limitation at the platform driver level.
This fixes SPI read errors observed on SandyBridge, IvyBridge, Haswell,
and Broadwell when reading option variables stored in SMMSTORE. When
scanning the store to locate a given variable, reads would often cross
into the next 4KiB page (eg, reading 60 bytes from 0x313ff0).
TEST=build/boot stumpy, link, beltino, jecht boards, verify no SPI read
errors in cbmem, CFR options work properly.
Change-Id: I73d9c0acdbbb2faf5caff1f73049bff900774156
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90689
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The smmstore_lookup_region() function was using
fmap_locate_area_as_rdev_rw() directly, which only provides
direct SPI access. This bypassed the optimized lookup_store()
function that uses incoherent_rdev to enable memory-mapped
reads via the read-only device while keeping direct SPI writes
via the read-write device.
Change smmstore_lookup_region() to call lookup_store() instead,
enabling memory-mapped reads for the public API and matching
the behavior of the internal implementation.
This improves read performance for EFI options and other
consumers of the SMMSTORE region device. It also fixes an issue
where direct SPI reads were crossing 4k page boundaries on older
platforms (Broadwell and earlier) causing them to fail and the
fallback option to be used, leading to a disconnect between the
user-selected option and device beahvior.
TEST=build/boot google/guado, verify all CFR options work properly
and no errors in cbmem.
Change-Id: I34947be932ede19a3fe896fe0da6373035fe6db7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
GCC's configure script requires gnat1, gnatbind, and gnatmake to be
available as unversioned executables in PATH when building with Ada
support. The previous detection logic only checked for gnat1 and used
a lenient searchtool check for gnatbind, which could incorrectly
enable Ada support when gnatmake was missing, causing configure to
fail with "GNAT is required to build ada".
In GNAT 15+, tools may only be available as versioned executables
(e.g., gnatbind-15, gnatmake-15), but GCC configure still requires
unversioned names. This change:
1. Adds explicit checks for gnatbind and gnatmake (unversioned)
2. Updates have_gnat() to require all three tools
3. Detects GNAT 15+ versioned tools and provides helpful error
messages with instructions to create symlinks
4. Falls back to generic installation instructions if no GNAT tools
are found
This prevents the configure error and provides clear guidance for
users with GNAT 15+ installations.
Change-Id: Idc16ec48612e88fc9bdd16b343ae267aa20490f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This reverts commit 14a7a2315e.
Reason for revert: The change causes DUT failed to resume from S3.
BUG=b:474254985
TEST=Wake up DUT by power key.
Change-Id: I2f2291a12d9b440d000a28e38bb590bc77a02c8a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
CB_MEM_TAG is considered as an reserved memory. But we want to mange
this region in the payload and release this region when MTE is inactive.
Add CB_MEM_TAG memory range to usedmem_ranges to get a page table
mapping and mark it as used.
BUG=b:438666196,b:474306129
TEST=Check the tag region is wiped out in DEV mode.
Change-Id: I498407cbd44b1cc70ef769a63b8e40665ea67b28
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90702
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The number of MCAX register used inside an MCA BANK changed from phoenix
onwards. Since phoenix all 16 MCAX register are used inside an MCA bank.
According to spec:
The MCA_SYND register stores a syndrome associated with the error logged
in MCA_STATUS or MCA_DESTAT. The “syndrome” may include syndrome values
associated with an error correcting code or other information about the
error. The contents of this register are valid if MCA_STATUS[SYNDV] bit
is set to 1 or MCA_DESTAT[SYNDV] bit is set to 1.
source: AMD64 Architecture Programmers Manual Rev 3.42
Change-Id: I20a31776d4b031c810ef0dc6502c421ade6f4315
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update the SoC USB driver to invoke mainboard_usb_typec_configure for
both primary and secondary ports. This is called after the QMP PHY
initialization to ensure the external signal path is correctly
muxed for the detected orientation.
BUG=b:473489095
TEST=Verify USB SS detection on Quartz.
Sample output:
```
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 00001203 00000000 00000000 00000000 ................
firmware-shell: md 0x0a600420 8
0a600420: 000002a0 00000000 00000000 00000000 ................
0a600430: 00001203 00000000 00000000 00000000 ................
```
Change-Id: Ic90a62b1f6ad62a8870c6d5333d06b6a11d26d4f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90711
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Implement mainboard_usb_typec_configure to program the Parade PS8820
retimers over I2C. The function sets the USB3 mode registers for
either normal or flipped orientation based on the polarity reported
by the SoC.
Additionally, update mainboard_init to perform standard I2C
initialization for the retimer buses when this feature is enabled,
ensuring the buses are ready for transactions during the USB
sequencing.
BUG=b:473489095
TEST=Verify USB SS detection on Quartz.
Sample output:
```
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 00001203 00000000 00000000 00000000 ................
firmware-shell: md 0x0a600420 8
0a600420: 000002a0 00000000 00000000 00000000 ................
0a600430: 00001203 00000000 00000000 00000000 ................
```
Change-Id: I14f86945aeea9b83a9433edd53f5023231ca859d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90707
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the MAINBOARD_HAS_PS8820_RETIMER Kconfig option. This will
be used to conditionally enable I2C initialization and retimer
configuration logic on Bluey variants.
BUG=b:473489095
TEST=Verify USB SS detection on Quartz.
Change-Id: I949fb16f8c46a8375b50d2b108b8edde3231f4e9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90710
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Add a function declaration for mainboard_usb_typec_configure. This
allows mainboards to implement custom logic for external components,
such as retimers or muxes, that need orientation-aware configuration.
BUG=b:473489095
TEST=Verify USB SS detection on Quartz.
Change-Id: I20d9a23da5b855a413f8358b8783f44c1632ccdf
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90709
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements the power-on and reset sequence for the USB-C1
retimer on the Bluey mainboard.
Sequence Details:
- romstage: Added early_setup_usb_typec to ensure all power rails
(3.3V, 1.8V, 0.9V) are disabled and the retimer is held in reset
early in the boot process.
- ramstage (mainboard): Added setup_usb_typec to perform the power-up
sequence with the required 1ms delays between rails to ensure
hardware stability:
BUG=b:473489095
TEST=Able to detect USB devices in HS mode.
Change-Id: Ia93c0078aecdec98f3af28e73e7af5af7a3b20d8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add spinlock synchronization to prevent concurrent SPI flash controller
access from multiple CPUs in SMP environments. The spinlock serializes
access to the SPI controller hardware in exec_sync_hwseq_xfer().
If SMP is not enabled, spinlock functions are no-ops, so this change
is safe for both SMP and non-SMP configurations.
This resolves an issue seen on the Starlabs Starfighter MTL where
multiple SPI transaction errors occurred when reading option variables
stored in SMMSTORE:
[ERROR] SPI Transaction Error at Flash Offset 103002a HSFSTS = 0x01016022
[ERROR] SPI Transaction Error at Flash Offset 1030004 HSFSTS = 0x01006022
[ERROR] SPI Transaction Error at Flash Offset 1030000 HSFSTS = 0x3f006022
...
Change-Id: Ic3003b0a986b587622102b6f36714bcb16c3d976
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The MIPI camera driver currently validates SSDB parameters for all
devices using the driver. However, some devices (VCM/NVM) does not have
these parameters configured.
Wrap the SSDB verification logic in a check for
`INTEL_ACPI_CAMERA_SENSOR`. This prevents the driver from throwing
"Parameters not set" errors and failing to create ACPI devices for
non-sensor devices.
BUG=b:474223827
TEST=Build and boot fatcat, verify that MIPI initialization no longer
fails for non-sensor MIPI devices while still enforcing validation for
actual camera sensors.
Change-Id: I34ef416cdc9fa35fdca21e9fecaa8d7fc2914338
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90697
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Convert MIPI camera configurations from static ASL files to devicetree-
based runtime ACPI generation using the mipi_camera driver. This moves
the camera IPU and device definitions from static ASL includes to
devicetree overridetree files.
Changes:
- Convert baseboard, voema, volteer, and volteer2 from static
mipi_camera.asl files to devicetree configuration
- Move IPU0 configuration with CAM0 and CAM1 to volteer/volteer2
variant overridetree files (baseboard devicetree not used directly)
- Remove all static ASL camera definition files (mipi_camera.asl)
- Simplify voema variant to use only 1 IPU port (CAM1 only) instead
of 2 ports, removing unused CAM0 port definition
- Add SSDB config based on sensor name/type and CIO2 config
This, along with follow-on patches, will allow volteer variants to be
properly supported under Windows/Linux as well as ChromeOS.
Change-Id: I7bd4ef2812a3d21b6541469bc3a126498d72f5ef
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The previous implementation violated ACPI spec by attempting to
implement a reset via _ON/_OFF, which are to be used exclusively for
device power management/power state transitions. As a result, under
Windows the CNVi BT device was continually re-enumerating and unable
to be used.
Fix this by moving the reset logic out of _ON/_OFF and into _RST, where
it belongs.
TEST=build/boot Win11 on google/taeko, verify BT device is functional.
Change-Id: I1627fefbf7747129344291cc8855c15dda50cf5f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90582
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add bulk_timeout() callback to USB controllers that allows to issue bulk
transaction with configurable timeout. This allows to peek if there is
any incoming data from USB device without needing to wait 5 seconds if
there is no data.
'finalize' argument is omitted in bulk_timeout(), because any recent
controller doesn't use it in bulk() method anyway. For OHCI and UHCI,
which are only controllers using 'finalize', issuing bulk_timeout() with
USB_MAX_PROCESSING_TIME_US timeout is the same as issuing bulk() with
'finalize' set to zero.
Change-Id: I82dbe307b566e4fc6cca314924168f7ad677efe7
Signed-off-by: Tomasz Michalec <tmichalec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90043
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
- Remove unused I2C3 pin configurations.
- Remove RST control. The ETU925 fingerprint module does not
need to control the RST pin.
BUG=b:452542491, b:467835297
TEST=emerge-ocelot coreboot
Change-Id: Ib4db733187d1b15f89654b53c1cf98420d652546
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90696
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
On AMD server systems there are multiple PCI root bridges. The root
bridge scanning in UEFI Payload is not sufficient to detect the
memory and I/O apertures properly. For example on Turin system, the
I/O aperture on the first root bridge containing the FCH may not
have any I/O resources detected on the PCI devices. This results in
the I/O decoding to be disabled on the root bridge, effectively
breaking the I/O based serial ports, e.g. on Super I/Os and BMCs.
Add new CBMEM ID to report the PCI root bridge aperture information
to the payload. The intention is to use the Universal Payload PCI Root
Bridges Info HOB that is already supported in the UEFI Payload. The HOB
will take priority over the root bridge scanning and properly report
the apertures of the PCI root bridges on AMD system.
Change-Id: If7f7dc6710f389884adfd292bc5ce77e0c37766f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Refactor code to use less redundant PCI accesses to decrease boot time.
Change-Id: Ic2bb610ebf22dd43580ac94360d905b1c782224a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90641
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
They are needed in a later patch which is not yet upstream.
source: AMD64 Architecture Programmers Manual Rev 3.42
Change-Id: I4f5bb5533d8f0e1765749d24ef0b22805ad1554a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90480
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
and USB-C1 Retimer I2C access
Load I2C firmware to QUPV3_0_SE3 and QUPV3_0_SE7 Serial Engines and
configure both in MIXED mode to enable I2C access for USB-C0 and USB-C1
retimers.
Test=
1. Created image.serial.bin and verified successful boot on X1P42100.
2. Read the corresponding QUP SE firmware revision read-only register
and confirmed that the protocol field (bits 8-15) matches the
programmed value. Register details are in HRD-X1P42100-S1
documentation:
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
Example:If programmed as I2C, the register value read is 0x00000303,
where 3 denotes the I2C protocol.
Change-Id: I337329628ac04246ab579e062a802a028cb4c560
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90690
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the battery state-of-charge print statement in romstage to
include a percentage symbol. This makes the log output more
readable and consistent with battery level reporting.
Use '%%' to correctly escape and print the literal '%' sign in
the printk statement.
BUG=None
TEST=Boot Bluey and verify romstage logs show "Battery
state-of-charge 95%" instead of "Battery state-of-charge 95".
Change-Id: I97b533567b56bfaba41508e35a6f324f0dbf331e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90684
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently _Exx suppots the wake pin under 255, for Caboc it's wake pin
is 325 which is out of range.
This CL change to use _EVT method to enhance GPIO event handling.
BUG=b:463410386
TEST=Compiled and tested on google/redrix and google/caboc:
1. emerge-brya coreboot, emerge-brox coreboot
2. Check /proc/interrupts has ACPI:Event
2. Wait for WWAN device to enter suspended state
3. Insert SIM card and modem is able to wake up WWAN device
Change-Id: Ifbb83ab48bbe4876269010adb2710641bdc879a5
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90492
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is going to be used by some devices, map the next available
extended code to it.
Change-Id: Ib4fc6c33e10f273a73f3a6ca40deeefa3ab70f20
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90617
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD_FW_GFXIMU_2 entry has the same type value as AMD_FW_SRAM_FW_EXT.
The tool may integrate one of these blobs incorrectly, because
it searches for the first entry of given type in the amd_psp_fw_table.
AMD_FW_GFXIMU_2 could have been added by mistake, because there is no
board that actually defines PSP_GFX_IMMU_FILE_2 in fw.cfg file.
Change-Id: I7e1f38c77156d06e9e6d801bdfa9b9eefcbb374e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90388
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The AMD_TA_IKEK occurrs twice in the amd_psp_fw_table, but the tool
will only add it once anyways, so remove redundant entry.
Change-Id: I7fd13552edf98d7adc749726c8bba46124aed495
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Use flexible array member cper_ia32x64_context to simplify the struct
usage.
Change-Id: I729cb914031b55b2b58bc9e459ee0ea15c7626e8
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90479
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor fsp_init to be called as a boot state entry
(BS_DEV_INIT, BS_ON_ENTRY) instead of directly from soc_init. This
ensures fsp initialization occurs at the appropriate boot stage.
This change is necessary for FW logo rendering in the ramstage. fsp_init
must be run before FW display starts rendering the logo.
BUG=b:471111147
TEST=Check FW logo
Change-Id: I41b32229d4c582d84afac5c336eb98b1b1274ba8
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
This patch adds config ARCH_RISCV_RV64 to support build of riscv64
payloads. New files under arch/riscv contain:
- Basic ldscript and payload entry point.
- Functions for riscv64 io and cache operations.
- Default timer code based on mtime delegation.
- Default cb_header_ptr passing with device tree to payload.
Change-Id: Ieb3d456d5edda87a3a4886ccfc17a7824c630427
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89646
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change Google's Rex touch device name from TH_SENSOR_GOOGLE to
TH_SENSOR_ELAN_REX to better reflect the specific vendor and platform
combination. This provides clearer identification and avoids generic
naming that could cause confusion with other Google touch
implementations.
BUG=none
TEST=This change cannot be tested in isolation as it only contains
naming changes. Testing requires hardware that supports Rex touchscreen
functionality, such as: Fatcat board with Google's specialized cable
connected to a Rex touchscreen. Verify that the new naming convention
works correctly with change:
https://review.coreboot.org/c/coreboot/+/89181 (This change uses the new
naming convention introduced here). Touch functionality should work
identically to before, with only the internal naming updated.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I40bb33dee14e9a567ad9dfcf956f3a9cca26dcad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90645
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
The KLED VBT file is misconfigured and results in an error under Linux:
[drm] ERROR VBT has malformed LFP data table pointers
Inspecting the VBT using the Intel BMP tool reveals invalid data for
many of the panel definitions, as well as other settings.
KLED works perfectly fine with the kindred VBT, so use that instead.
TEST=build/boot Win11/Linux on KLED, verify display output works
properly.
Change-Id: I09aaa5c17517633fdae508239ecf8e72e3990e33
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90637
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Starting with Turin there are 8 IOHCs per SoC. Add new definitions
for the missing IOHCs. Based on Turin C1 PPR (doc 57238).
Change-Id: I31e93e680e3f0ba03d2595f632d6827b4e3042b8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90368
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Strip quotes from CONFIG_AMDFW_CONFIG_FILE, otherwise the IF condition
may not catch the case when CONFIG_AMDFW_CONFIG_FILE is an empty string.
TEST=Omit PSP blobs when building coreboot for Gigabyte MZ33-AR1 by
clearing the AMDFW_CONFIG_FILE path.
Change-Id: I1ecf61844c03c89b3429e23936172f79c8d4b2f4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90367
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add PCI I/O-based SMN accessors. These accessors can be used for
early workarounds when the PCI ECAM MMCONF is not working yet.
An example of such workaround is the patching of PCI ECAM MMCONF
base address in Turin SoC, which has to be done via SMN, but it
cannot use PCI ECAM MMCONF to access SMN yet.
Change-Id: I5e0faaa48e4d7b4479e3af9b795ad2a879f569fd
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the support RAM parts for gothrax.
Here is the ram part number list:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H58G56AK6BX069 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
H9JCNNNBK3MLYR-N6E 0 (0000)
H9JCNNNCP3MLYR-N6E 3 (0011)
K3KL8L80CM-MGCT 4 (0100)
RS1G32LO5D2FDB-23BT 5 (0101)
BUG=b:472596025
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Iff12898dd6fb08a7e932de6e1902886a6f251761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add support to enable MMCX power rail and vote for MM0 BCM resource
required for display. This change includes support to enable display
clocks.
TEST= 1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified MMCX rail enablement and MM0 BCM vote using ARC and
BCM AOP dump.
Serial Log:
[INFO ] RPMH_REG: Initialized mmcx.lvl at addr=0x30080
[INFO ] ARC regulator initialized successfully
[DEBUG] RPMH_REG: Sent active request for mmcx.lvl
[INFO ] ARC level has been set successfully
[DEBUG] BCM: Found address 0x00050024 for resource MM0
[INFO ] BCM: Successfully voted for MM0 (addr=0x00050024, val=0x60004001)
[INFO ] BCM vote for MM0 sent successfully
3. Verified if the clocks are enabled by taking clock dump. Clock
enablement is verified by dumping the 31st bit of the corresponding
clock’s CBCR register. A value of 0 in bit 31 indicates that the clock
is ON. The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
Change-Id: I89715fb4e3a6122388068a819e24cb409e204155
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90507
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add API to initialize RPMh resources for display. It includes CMD-DB
initialization, enable the MMCX power rail and cast a vote for the MM0
Bus Clock Manager (BCM) resource to enable display clocks.
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified MMCX rail enablement and MM0 BCM vote using ARC and
BCM AOP dump with API invoking changes hooked up with follow-on
commits.
Serial Log:
[INFO ] RPMH_REG: Initialized mmcx.lvl at addr=0x30080
[INFO ] ARC regulator initialized successfully
[DEBUG] RPMH_REG: Sent active request for mmcx.lvl
[INFO ] ARC level was set successfully
[DEBUG] BCM: Found address 0x00050024 for resource MM0
[INFO ] BCM: Successfully voted for MM0 (addr=0x00050024, val=0x60004001)
[INFO ] BCM vote for MM0 sent successfully
Change-Id: I1997ce7a1ced4504d6a3170e5f2ddd4f52e0763d
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90467
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add RPMh driver support, introducing the core driver that provides
an interface to the RPMh protocol for managing ARC/VRM/BCM type
resource requests. This includes basic TCS (Trigger Command Sets)
handling and helper functions for sending RPMh requests.
RPMh (Resource Power Manager – hardware) is a protocol that enables
processors (e.g., APSS, LPASS) to send power-related commands to the
RPMh hardware block. Dynamic management of power and clocks for shared
resources is handled either directly by hardware or by RPM.
Key features include:
- Core infrastructure for submitting TCS (Trigger Command Sets)
commands to the RPMh.
- Regulator driver using RPMh for LDOs and SMPS control.
- BCM (Bus Clock Manager) voting for clock resources.
Test=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I1f85459c68d0256e15765b0716856dc928080df9
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
