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coreboot_tables: Add new CBMEM ID to hold the PCI RB aperture info

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On AMD server systems there are multiple PCI root bridges. The root
bridge scanning in UEFI Payload is not sufficient to detect the
memory and I/O apertures properly. For example on Turin system, the
I/O aperture on the first root bridge containing the FCH may not
have any I/O resources detected on the PCI devices. This results in
the I/O decoding to be disabled on the root bridge, effectively
breaking the I/O based serial ports, e.g. on Super I/Os and BMCs.

Add new CBMEM ID to report the PCI root bridge aperture information
to the payload. The intention is to use the Universal Payload PCI Root
Bridges Info HOB that is already supported in the UEFI Payload. The HOB
will take priority over the root bridge scanning and properly report
the apertures of the PCI root bridges on AMD system.

Change-Id: If7f7dc6710f389884adfd292bc5ce77e0c37766f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Michał Żygowski 2025-10-06 11:53:10 +02:00 • committed by Matt DeVillier
commit c7f0697867
3 changed files with 5 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
View file

@ -92,6 +92,7 @@
#define CBMEM_ID_AMD_OPENSIL 0x4153494C
#define CBMEM_ID_PVMFW 0x666d7670
#define CBMEM_ID_BOOT_MODE 0x444D5442
#define CBMEM_ID_RB_INFO 0x50524249
#define CBMEM_ID_TO_NAME_TABLE \
{ CBMEM_ID_ACPI, "ACPI " }, \
@ -176,5 +177,6 @@
{ CBMEM_ID_CSE_BP_INFO, "CSE BP INFO"}, \
{ CBMEM_ID_AMD_OPENSIL, "OPENSIL DATA"}, \
{ CBMEM_ID_PVMFW, "PVMFW "}, \
{ CBMEM_ID_BOOT_MODE, "BOOT MODE "}
{ CBMEM_ID_BOOT_MODE, "BOOT MODE "}, \
{ CBMEM_ID_RB_INFO, "PCI RB INFO"}
#endif /* _CBMEM_ID_H_ */

1
src/commonlib/include/commonlib/coreboot_tables.h
View file

@ -90,6 +90,7 @@ enum {
LB_TAG_EFI_FW_INFO = 0x0045,
LB_TAG_CAPSULE = 0x0046,
LB_TAG_CFR_ROOT = 0x0047,
LB_TAG_ROOT_BRIDGE_INFO = 0x0048,
/* The following options are CMOS-related */
LB_TAG_CMOS_OPTION_TABLE = 0x00c8,
LB_TAG_OPTION = 0x00c9,

1
src/lib/coreboot_table.c
View file

@ -274,6 +274,7 @@ static void add_cbmem_pointers(struct lb_header *header)
{CBMEM_ID_FMAP, LB_TAG_FMAP},
{CBMEM_ID_VBOOT_WORKBUF, LB_TAG_VBOOT_WORKBUF},
{CBMEM_ID_TYPE_C_INFO, LB_TAG_TYPE_C_INFO},
{CBMEM_ID_RB_INFO, LB_TAG_ROOT_BRIDGE_INFO},
};
int i;