erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

include/cpu/x86/msr.h: Add MCA related MSRs

Browse source 
They are needed in a later patch which is not yet upstream.

source: AMD64 Architecture Programmers Manual Rev 3.42

Change-Id: I4f5bb5533d8f0e1765749d24ef0b22805ad1554a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90480
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maximilian Brune 2025-11-28 15:31:28 +01:00 • committed by Felix Held
commit 1da7c31810
2 changed files with 16 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

15
src/include/cpu/x86/msr.h
View file

@ -40,9 +40,12 @@
#define IA32_SMM_MONITOR_CTL_MSR 0x9B
#define SMBASE_RO_MSR 0x98
#define IA32_SMM_MONITOR_VALID (1 << 0)
#define IA32_SYSENTER_EIP 0x176
#define IA32_MCG_CAP 0x179
#define MCG_CTL_P (1 << 8)
#define MCA_BANKS_MASK 0xff
#define IA32_MCG_STATUS 0x17A
#define MCG_STAT_EIPV (1 << 1)
#define IA32_PERF_STATUS 0x198
#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
@ -74,6 +77,8 @@
#define MCA_STATUS_HI_ADDRV (1UL << (58 - 32))
#define MCA_STATUS_HI_PCC (1UL << (57 - 32))
#define MCA_STATUS_HI_COREID_VAL (1UL << (56 - 32))
#define MCA_STATUS_HI_TCC (1UL << (55 - 32))
#define MCA_STATUS_HI_SYNDV (1UL << (53 - 32))
#define MCA_STATUS_HI_CECC (1UL << (46 - 32))
#define MCA_STATUS_HI_UECC (1UL << (45 - 32))
#define MCA_STATUS_HI_DEFERRED (1UL << (44 - 32))
@ -172,6 +177,16 @@ static inline int mca_pcc(msr_t msr)
return !!(msr.hi & MCA_STATUS_HI_PCC);
}
static inline int mca_tcc(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_TCC);
}
static inline int mca_syndv(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_SYNDV);
}
static inline int mca_idv(msr_t msr)
{
return !!(msr.hi & MCA_STATUS_HI_COREID_VAL);

4
src/security/intel/txt/txt_register.h
View file

@ -3,6 +3,7 @@
#ifndef SECURITY_INTEL_TXT_REGISTER_H_
#define SECURITY_INTEL_TXT_REGISTER_H_
#include <cpu/x86/msr.h>
#include <types.h>
/*
@ -162,9 +163,6 @@
#define ACM_FORMAT_SIZE_128KB (128 * KiB / 4)
#define ACM_FORMAT_SIZE_256KB (256 * KiB / 4)
/* MSRs */
#define IA32_MCG_STATUS 0x17a
/* DPR register layout, either in PCI config space or TXT MMIO space */
union dpr_register {
struct {