MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction
ACK from SPM: 0, non-SPM: 0x1.
In MT8196, SPM has masked all the DDR requests, so this setting should
be set to non-SPM whenever mminfra is powering on. Otherwise, GCE will
hang when accessing DRAM.
BUG=b:379039600
TEST=boot up ok, GCE can access DRAM continuously
Change-Id: I30309b0426f803e28858eb15652a649927f94c7e
Signed-off-by: Jason-jh Lin <jason-jh.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
In the current eDP initialization flow, eDP is configured and enabled
before display data pipe (DDP) initialization. The init flow is wrong,
because eDP should be enabled only after DDP is correctly set up. The
wrong flow may lead to garbage display between enabling eDP and
configuring DDP.
To fix the problem, the dptx_video_enable(true) call needs to be moved
after mtk_ddp_mode_set(). Introduce a new API mtk_edp_enable() for eDP
enablement, to be separated from the existing mtk_edp_init(). The fixed
eDP init flow is: mtk_edp_init -> mtk_ddp_mode_set -> mtk_edp_enable.
Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86028
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Run mtk_fsp_romstage.elf (MediaTek firmware support package for
romstage) in romstage to support power switch.
BUG=b:373797027
TEST=build pass, boot ok.
Load and run mtk_fsp with following logs:
[DEBUG] FMAP: area FW_MAIN_A found @ 402000 (1527552 bytes)
[INFO ] CBFS: Found 'fallback/mtk_fsp_romstage' @0xfc280 size 0x6bd in
mcache @0x00122518
[INFO ] VB2:vb2_digest_init() 1725 bytes, hash algo 2, HW acceleration
enabled
[INFO ] _start: MediaTek FSP_ROMSTAGE interface version: 1.0
[INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_romstage at phase
0x30 done
Change-Id: Id223152e0bda71e99e72b34c91fea8f8841e824b
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86015
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Unlike MT8186/MT8188/MT8192/MT8195, MT8196 has 5 EINT base registers,
each with a different number of EINT bits. In preparation for the
upcoming MT8196 EINT unmasking support, replace the `eint_event_reg`
struct (which has a hardcoded register number) with an array
`eint_event` to specify the EINT base register(s).
BUG=none
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: I86fd3109c9ff72f33b9fea45587d012b003a34ba
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86033
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Load MCUPM firmware and boot up MCUPM in ramstage.
It takes 54 ms to load mcupm.bin.
coreboot logs:
CBFS: Found 'mcupm.bin' @0x37a80 size 0xdbda in mcache @0xfffdd308
mtk_init_mcu: Loaded (and reset) mcupm.bin in 54 msecs (486931 bytes)
TEST=Build pass and we can see the mcupm logs after reset releases.
BUG=b:317009620
Change-Id: I223f245d384f32d54f6170a28b29573638f77296
Signed-off-by: Agogo Huang <agogo.huang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This resolves a crash issue observed on Meteor Lake and introduced by
commit 70bdd2e1fa ("cpu/x86/topology:
Simplify CPU topology initialization"). This commit simplifies the
code and provides more detailed CPU topology information by
generalizing the use of the Extended Topology Enumeration Leaves
0x1f. As a result, the coreboot APIC core_id field does not provide
the fully detailed path information.
It turns out that the topology core identifier is used by the coreboot
MP service mp_get_processor_info() implementation. But the MP Service
EFI_CPU_PHYSICAL_LOCATION data structure only captures information
about the package, core, and thread. The core identifier returned to
the MP service caller must incorporate the full hierarchical path (die
group, die, module, tile, module and core).
This commit adds a new field to the cpu topology structure to
represent the core ID within the package.
For reference, here is that signature of the crash:
LAPIC 0x40 in X2APIC mode.
CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting
Code: 0 eflags: 00010046 cr2: 00000000
eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000
edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0
[...]
The crash occurred when FSP attempted to lock the Protected
Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL
0x4e).
69f3d1d3: 8b 43 f4 mov -0xc(%ebx),%eax
69f3d1d6: 89 4d c4 mov %ecx,-0x3c(%ebp)
69f3d1d9: 89 45 dc mov %eax,-0x24(%ebp)
69f3d1dc: 8b 55 c4 mov -0x3c(%ebp),%edx
69f3d1df: 8b 45 c0 mov -0x40(%ebp),%eax
69f3d1e2: 8b 4d dc mov -0x24(%ebp),%ecx
69f3d1e5: 0f 30 wrmsr
69f3d1e7: e9 ee fd ff ff jmp 0xfffffe39
FSP experiences issues due to attempting to lock the same register
multiple times for a single core. This is caused by an inconsistency
in the processor information data structure, where multiple cores
share the same identifier. This is not permitted and triggers a
General Protection Fault Exception.
TEST=Executing CpuFeaturesPei.efi in FSP-S does not crash on a rex
board.
Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86004
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Improve host EC command debugging with timestamps and duration for
better analysis, this feature can be enabled by selecting the config
EC_GOOGLE_CHROMEEC_HOST_CMD_DEBUG.
BUG=none
TEST=Brox/lotso device successfully built and booted. Debug messages
confirmed in device logs only when the specific configuration is
selected. Sample print: "EC HOST CMD Duration: 661 us, Command: 0x4b,
version: 0x0"
Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch selects the ISH main firmware Kconfig to prevent
google/fatcat from trying to retrieve a dummy ISH SHIM firmware version,
since ISH FW in google/fatcat will be part of the kernel firmware image.
BUG=b:370984186
TEST=Build and boot google/fatcat, config exists in coreboot.config
Change-Id: Id24394cb6c6dbaed13c87612da341e47eb69895f
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85920
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit e24294ff9ade ("lsusb -t: print ports and busses and devices with
same width") [1] in the usbutils repository changed the format of the
lsusb -t output, breaking the find_usbdebug.sh script. This commit is
present in usbutils version 016 and later.
Use the output of lsusb -V to set the parsing patterns based on the
version in order to maintain compatibility with older versions of
usbutils. A simple integer comparison of the version number is used for
this, which will not work with versions older than v001 as those use a
0.nn version number format. However, since v001 was released in late
2010, it is probably safe to assume that no one will be using a version
of usbutils older than that. Usbutils v016 was released in late 2023 so
there could still conceivably be systems using older versions, such as
Ubuntu 22.04 LTS which is on v014.
TEST=find_usbdebug.sh works as expected with both lsusb v015 and v017
[1] e24294ff9a
Change-Id: Iffa1238b995d387d6e51459f85ae96da52a5c0ff
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85790
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Since Python 3.12, invalid escape sequences produce a SyntaxWarning;
in the future, they will produce SyntaxError.
Using raw strings clear out the warning.
Below the command used for checking the fix worked.
```
$ python3 util/lint/checkpatch_json.py
```
Link: https://docs.python.org/3.12/whatsnew/3.12.html#other-language-changes
Change-Id: I0177dc7f0d3013759879320afdb6ab548d356bc7
Signed-off-by: Ariel Otilibili <otilibil@eurecom.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85771
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
While I don't have +2 rights, I think it makes sense to add myself as
maintainer given I'm a creator of both ports in upstream tree.
Change-Id: I2484fc488040c2d86bbf3bf98f39354bf88efae8
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add a check to make sure lsusb and lspci are installed, as the script
relies on them to function properly. Previously, if lsusb was not
installed, the script proceeded as if nothing was wrong, but never found
any devices plugged into the debug port. If lspci was not found, the
script exited saying that no EHCI debug capable controller was found.
The "command not found" messages that normally would have been shown in
these situations was not being shown, as stderr is redirected to
/dev/null to hide error messages that don't matter as per the comment
near the top of the script.
Change-Id: Ib56a20aab9552aa6321c2fb9ad0d2ca7d6cd00c7
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Commit ce10b6f821 unhid the BOOT0000
device from Windows. It requires a driver that's available from Coolstars EC bundle.
Guard this against the ChromeEC, so that non-Chromebooks don't get an
error device in Device Manager.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6645c1be7d602a2775f703f5cf56e4c9d6f3bb76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Rather than unconditionally returning that the device is present,
return whether the fTPM is on or not.
Test=Boot the StarLite Mk V with the Intel ME disabled, and check
that the TPM is reported as not present.
Change-Id: If8236021bf0e1264646971cff9c998fac99ac220
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85228
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The CLFR method exists outside the CNVi device, so add `^` to allow
it to be found. This fixes the SSDT and allows the method to be used.
TEST=build/boot starlabs/starlite_adl
Change-Id: I1158cf1ccf50d9095fdab8d2d663041ef1985513
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The DPTF parameters were defined by the thermal team.
Based on thermal table in 377955793#comment20
BUG=b:377955793
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I0455d62a9f174fd911e5aa0b9626329ad2ac8f06
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86000
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
There is an issue where the codec enable signal is not working correctly
when FPS (Fingerprint Sensor) is enabled. This commit applies a
temporary workaround by using a dedicated GPIO pin for codec enable.
This allows the codec to function properly even when FPS is enabled,
preventing audio issues. A proper fix in hardware schematics will be
implemented in a future update.
BUG=b:390031369
TEST=Verified audio playback works with FPS being enabled.
Change-Id: I9883036b5e964cb55bd34c36398a501f69a8ecaa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
The file chromeos-debug-fsp.fmd is no longer needed, as the FMD
configuration is now handled by the generic Chrome OS FMD file.
This change removes the file to simplify the build process and
reduce the amount of code that needs to be maintained.
Change-Id: Ida430d415ae3f7dc93b89eb4d7c7ba59ed280e1b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85971
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
dt_find_node() calls dt_read_cell_props() for every node it walks, but
this is only actually necessary when the caller is interested in the
`#address-cells` and `#size-cells` values and passed out-parameters to
receive them. Most callers don't actually do that, and we scan through
all properties needlessly on every node. This patch adds a fast path to
skip that.
Change-Id: I114f824a7d88b0bac4a96aca3f7dced459503b02
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85989
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This patch wraps `dt_find_node()` in a function that initializes the
addr_cells and size_cells values to the defaults provided in the FDT
specification before potentially updating them from found values, so
that we always return the correct result and remove the burden of
correctly initializing them from the caller.
Change-Id: I39ba2c82d3a0d0b39a2ed5eba2420a04fbccb2f7
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85988
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
In Flattened Device Trees, there exist special properties called
`#address-cells` and `#size-cells` that determine how large addresses
and sizes in `reg` properties are. According to the FDT specification,
each `reg` node cares about the `...cells` property in the _parent_ of
its node. Our current implementation looks for those properties in the
node it finds and returns, which would presumably be the node with the
`reg` property itself. Therefore, we're returning the wrong `...cells`
values.
This isn't really a problem in practice because we also allow inheriting
these properties from the parent when they don't exist in the child, and
nodes that contain `reg` properties usually don't contain `...cells`
properties themselves (because those properties would be incorrect and
useless there), so we usually just end up falling back to the (correct)
value we inherited from the parent. But it's still better to just fix
the mistake, and if we ever happen to have a situation where the node
containing the `reg` property still has children that require different
`...cells` values as well, it could make a difference. (The fact that
we're inheriting these properties is also technically incorrect
according to the spec, but we're doing that intentionally to match
behavior in the Linux kernel.)
This issue was already correctly implemented in the recently added
fdt_find_node() from commit 33079b8174 ("lib/device_tree: Add some FDT
helper functions"), and this patch also fixes it in the older
dt_find_node().
Change-Id: I323066477a4d4be17225e0915a81ce2ff39c1e40
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85964
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
mt6373_init_pmif_arb() needs to be initialized for SD card to control
the regulator.
TEST=emrege-rauru coreboot
TEST=The assertion is gone on Rauru during normal boot.
Change-Id: I7e3265bb62a6c78d44e2c756be9a020a49a03056
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85969
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Return to the caller immediately if pmif_arb has been initiailized. In
this way, we can skip unnecessary check and reduce the access to the
PMIF register.
TEST=emerge-geralt coreboot && emerge-rauru coreboot
Change-Id: Id1d11f8b238855edb393d77151159792e7716d22
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This has always been set in downstream defconfig's; remove it here
to avoid build issues with Jenkin's being unable to find a suitable
EC binary.
Change-Id: I02a10211d7cec9a2c8a0837f77ca17acdcb06c22
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add Kconfig options for `_SB`, the smart battery variant which
is identical apart from a different EC which supports a Smart
Battery instead of the CW2015.
Change-Id: I1e04ea26ef597ce542a7348982d056fb55de0d22
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The selected options were a bit illogical, so but them all under
the common board Kconfig, alphabetise and dedpulicate them.
Change-Id: I277249323e8735dda0a6e394e475435ddedf5537
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85972
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
