The TPM related files were moved into src/security/tpm in commit
64e2d19082 ("security/tpm: Move tpm TSS and TSPI layer to security
section"), then further work was done on the coreboot TPM stack which
makes it difficult to find the equivalent area of code which these files
correspond to.
Therefore, we will drop these files for now and leave it up to the
maintainers of VBOOT to re-add any TPM related files (if they want to)
in a future change.
Change-Id: Ief7cfb81efc4c3daadc4b73af21bfdf0224b9005
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit 4f13f72dbc ("libpayload: Define UCHAR_MAX/CHAR_MIN/CHAR_MAX").
Reason for revert: char can be either signed or unsigned. If it's
unsigned, then CHAR_MIN would be incorrectly defined as 128.
Change-Id: Id49ddfff2d91029dc191b8b64e8e3f325ad0a462
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89469
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ReportingPchPmDisableEnergyReport has been 0 by default in all
FSP versions up until Meteor Lake. Set this to unify the
configuration between boards.
No applicable tests.
Change-Id: If9cdbb466bf8e4efc7a1577b0a1fec6270550d05
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89527
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only PmcLpmS0ixSubStateEnableMask is currently configured, and
PmcPchLpmS0ixSubStateEnableMask is left with the default value.
These should be the same.
Change-Id: I71bebec251c5c336407c2c173af29ddbfde0691b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These do not need to be configured, as they're configured
automatically on reset.
Change-Id: I26c9a42fa44b55208583859895f9a39016e76eac
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89523
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces necessary changes to correctly initialize the
Qualcomm X1p42100 USB4/DP PHY based on the USB Type-C CC polarity
detection.
When a Type-C cable is connected, the CC lines determine the
connector orientation (polarity). The USB PHY lanes must be swapped
accordingly to ensure the SuperSpeed signals are routed correctly.
Key changes:
- Adds 'get_usb_typec_polarity()' to read the CC polarity state from
the PMIC (SMB1/SMB2) via the 'SCHG_TYPE_C_MISC_STATUS' register.
- Extends 'qmp_usb4_dp_phy_ss_init()' to accept a 'polarity_inverse'
boolean.
- Uses the polarity state to set the 'SW_PORTSELECT' register in the
USB4/DP common configuration, effectively swapping the lanes when
needed.
- Calls the updated PHY initialization function with the appropriate
polarity for both primary (SS0) and secondary (SS1) USB instances.
This ensures robust USB functionality regardless of the cable insertion
orientation.
BUG=b:448107633
TEST=Verify USB-C works in both polarities on Google/Quenbi.
Without this CL -
USB3 key doesn't work in inverted polarity.
With this CL -
USB3 key works in both polarities.
Change-Id: I1855a12e32a76032d4c1b57770143c152b806008
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Enhancements have been made to the Intel touch driver, including support
for Google touchscreen devices, ELAN9006 and ELAN6918. The update
also includes device-specific configuration changes for both I2C and SPI
interfaces.
Key improvements include:
- Google Touchscreen support integration for ELAN9006 (SPI) and ELAN6918
(I2C).
- Specification of recommended connection speeds for supported devices.
- Removal of an unnecessary 100ms delay in the SPI _RST method.
- Addition of a function to map the System on Chip's (SoC) I2C speed
frequency.
- Improved device-specific connection speed settings for both I2C and
SPI interfaces.
These changes aim to improve the driver’s compatibility and efficiency
when interacting with the newly supported devices.
BUG=none
TEST=Test the updated driver on devices using ELAN9006 and ELAN6918 to
verify improved responsiveness and correct device initialization.
Confirm that connection speeds are set as recommended and check the
absence of the previously unnecessary delay in SPI operations from the
SSDT.
Change-Id: Ie35de90ece44101aea008d13d19e12873cdc09bf
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit makes the tile and die ID CPU topology parameters
information available to support the implementation of
EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo() in accordance with the
Platform Initialization Specification 1.7.
TEST=Instrumentation shows that the tile_id and die_id apic_path fields
are properly populated.
Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d64
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89461
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When configuring the touch_thc_i2c controlled touchpad and touchscreen
for the first time, referring to the fatcat code. The touchpad and
touchscreen could not be successfully bringup, since the touchpad and
touchscreen configured in the code are opposite to those in the fatcat
schematic diagram. According to the circuit schematic
NB7835CAA_SCH_MB_V1_A.pdf, modify the GPIO configuration and devicetree.
1. Configure GPIO as THC-I2C function.
2. Modify devicetree
touchpad ==> THC0
touchpanel ==> THC1
BUG=b:448030832 b:445817408
TEST=emerge-fatcat coerboot chromeos-bootimage
flash to DUT, touchpad and touchpanel can be found by `getevent`
Change-Id: I6826145f58d437e03683a4459ded3b7657cf616a
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89383
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the PinMux is configured correctly, these no longer
need to be set, as they're configured automatically on reset.
Change-Id: I03c6431f6ce7118444ef3672de32c5afa2e36441
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
When the board uses OpenSIL, the OpenSIL include paths already include
the $(top). Vboot patches the paths so that all of them include $(top)
at the beginning. This however would result in the include paths from
OpenSIL to include $(top) twice. Filter the paths that already contain
the $(top) and strip the prefix. Then add the $(top) prefix again to
all include paths to fix the problem.
TEST=Build vboot lib selected by enabled measured boot on Gigabyte MZ33-AR1.
Change-Id: Id67ea760f7b1ee2212f19a875c905771cdecdfa5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89114
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the Meteor Lake SoC configuration to select the
`FSP_DIMM_INFO` Kconfig option. This change instructs the build system
to use the common FSP driver implementation for retrieving and storing
DIMM information.
As a result, the duplicated, SoC-specific DIMM information retrieval
logic is dropped from the Panther Lake SoC code base, centralizing
the memory parsing mechanism.
TEST=Able to build and boot google/screebo. Verify the memory related
information is proper as part of the SMBIOS table.
Change-Id: I88fe72b558d2f9af55b585fd20f5f55e15eb465f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89496
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the Panther Lake SoC configuration to select the
`FSP_DIMM_INFO` Kconfig option. This change instructs the build system
to use the common FSP driver implementation for retrieving and storing
DIMM information.
As a result, the duplicated, SoC-specific DIMM information retrieval
logic is dropped from the Panther Lake SoC code base, centralizing
the memory parsing mechanism.
TEST=Able to build and boot google/kinmen. Verify the memory
related information is proper as part of the SMBIOS table.
Change-Id: I3323d3add9213cc384b9a2ca978681287d0e1822
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch extracts the implementation responsible for retrieving DIMM
information from the FSP HOBs and centralizes it within the common FSP
driver code.
This ensures that each SoC layer does not duplicate the logic for
parsing memory-related data. The primary goal is to rely on the
common FSP driver code for retrieving memory information.
The only SoC-specific implementation that remains is limited to
handling dependencies related to FSP UPD or header differences across
SoC generations.
TEST=Able to build and boot google/kinmen. Verify the memory related
information is proper as part of the SMBIOS table.
Change-Id: Ic3741a248bb1fe9420c784d51fbf459a30f8c42f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89494
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable clocks for Type-C ports C0 and C1.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
BUG=b:448107633
TEST = Verified that all the clocks added are ON during usb init.
BIT31[CLK OFF] of CBCR register of respective clock indicates
clock status.
Clock Configuration Status:
Clock Name State Register Value
----------------------------------------------------------------
gcc_usb30_mp_master_clk ON 0x00117018 0x00000001
gcc_usb30_mp_sleep_clk ON 0x00117024 0x00000001
gcc_usb30_mp_mock_utmi_clk ON 0x00117028 0x00000001
gcc_usb3_mp_phy_aux_clk ON 0x00117288 0x00000001
gcc_usb3_mp_phy_com_aux_clk ON 0x0011728C 0x00000001
gcc_usb3_mp_phy_pipe_0_clk ON 0x00117290 0x00000001
gcc_usb3_mp_phy_pipe_1_clk ON 0x00117298 0x00000001
gcc_cfg_noc_usb3_mp_axi_clk ON 0x001173CC 0x00000001
gcc_aggre_usb3_mp_axi_clk ON 0x001173D0 0x00000001
gcc_sys_noc_usb_axi_clk ON 0x0012D014 0x00000001
gcc_cfg_noc_usb_anoc_north_ahb_clk ON 0x0012D028 0x00000000
gcc_cfg_noc_usb_anoc_south_ahb_clk ON 0x0012D02C 0x00000000
gcc_aggre_usb_noc_axi_clk ON 0x0012D034 0x00000001
gcc_cfg_noc_usb_anoc_ahb_clk ON 0x0012D024 0x00000000
gcc_usb30_prim_master_clk ON 0x00139018 0x00000001
gcc_usb30_prim_sleep_clk ON 0x00139024 0x00000001
gcc_usb30_prim_mock_utmi_clk ON 0x00139028 0x00000001
gcc_usb3_prim_phy_com_aux_clk ON 0x00139064 0x00000001
gcc_usb3_prim_phy_pipe_clk ON 0x00139068 0x00000001
gcc_cfg_noc_usb3_prim_axi_clk ON 0x0013908C 0x00000001
gcc_aggre_usb3_prim_axi_clk ON 0x00139090 0x00000001
gcc_cfg_noc_usb3_sec_axi_clk ON 0x001A108C 0x00000001
gcc_aggre_usb3_sec_axi_clk ON 0x001A1090 0x00000001
gcc_usb30_sec_master_clk ON 0x001A1018 0x00000001
gcc_usb30_sec_sleep_clk ON 0x001A1024 0x00000001
gcc_usb30_sec_mock_utmi_clk ON 0x001A1028 0x00000001
gcc_usb3_sec_phy_aux_clk ON 0x001A1060 0x00000001
gcc_usb3_sec_phy_com_aux_clk ON 0x001A1064 0x00000001
gcc_usb3_sec_phy_pipe_clk ON 0x001A1068 0x00000001
Change-Id: I86cd84f515a22a080fe39687c8b7b8c01cb9c001
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89350
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This doesn't do anything, so remove it.
Change-Id: Ic753d0f08bdc0e9dd839357eb73c9771d94e5c83
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
There are three options for the LID switch:
SWITCH_NORMAL 0x00
SWITCH_SLEEP_ONLY 0x01
SWITCH_DISABLED 0x02
Add these to coreboot to ensure they are set correctly.
Change-Id: I159111438eabd4abeb654be75fd80f29bd835055
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure Pin Mix for Cs, Clk, Miso and Mosi to get the eSPI
GPIOs working as they should be.
Change-Id: I798f1e98f611a53e9c87f15e1e0f1679b9933bee
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89520
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common settings are:
* Reorder Child Device mappings to prioritise EFP displays.
* Disable EFPx that are not present.
* eDP panel colour depth is 24-bit (8 bpc).
* POST brightness of 100.
* Minimum brightness of 0.
* DPST level of 2.
* PSR Enabled.
* DDRS Enabled.
Test=Boot all boards, check brightness levels are consistant, the
kernel recognises that PSR and DDRS are enabled, check all outputs
work.
Change-Id: I7eb6a110d25d4bcfd26ffdddd9ec666fc90a04b0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89515
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The macro USB2_PORTS_MID vs USB2_PORTS_TYPE_C essentially enables
or disables the PortResetMessage. This is only relevant to TCSS
ports.
Correct the macros accordingly.
Change-Id: I18a078c7f6fb937293e6159f05587b7e1f881512
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89513
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This isn't supported so remove it.
Change-Id: I8e8a87f1394199d3288ae27601069ad88e2fa74f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The IRQ97 will continue to be triggered, and cros_ec_irq_thread()
will be called all the time, even if GPP_E07 is high.
The following information will be continuously printed on the EC
console:
25-09-20 15:25:53.945[148.780609 HC 0x0067 err 9]
...
According to NB7835CAA_SCH_MB_V1_A.pdf,
change
PAD_CFG_GPI_SCI_LOW(GPP_E07, NONE, DEEP, LEVEL),
->
PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
can fix the interrupt exception.
BUG=b:445883867
TEST=emerge-fatcat coreboot and there is no HC error storm.
Change-Id: Ic151dce7881a6730a347eeae8f2e029fdc60bbd0
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89362
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This also adds a missing trailing '/' to util/gitconfig, as this is a
directory.
Change-Id: Ib45dbf161b773cd89ad5acee183aeceac4d29584
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89506
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was moved to commonlib in commit dc9f5cd546 ("coreboot: introduce
commonlib"), then subsequently moved into commonlib/bsd in
commit ea619425ee ("commonlib: Move commonlib/cbmem_id.h to commonlib/bsd/").
Change-Id: Ib92c89cd090e78c76931000925ea6292e1783e28
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89510
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was renamed to util/qualcomm in commit 101098c41a
("sdm845: Combine BB with QC-Sec for ROM boot").
Change-Id: I14c9b6d918d30e1d156559d110ad47e556645d84
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Add the Elan touchpad configuration for moonstone AVL.
BUG=b:442964901
TEST=build firwmare and check the touchpad can work well in ALOS.
cat /sys/bus/i2c/devices/i2c-12/i2c-ELAN0000\:00/name
i2cdetect -y -r 12 -> 0x15 = UU
Change-Id: Ie105906fb54383dbf91513f81ab933653162ad4e
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89467
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the focaltech
touchscreen (FTSC1000) device, connected to I2C bus 38.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:442964901
TEST=emerge-fatcat coreboot and focaltech touchscreen can work well.
Change-Id: I7fb2f8b3c4ceb9d4bc7471d7eef23b0a18dca78a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89465
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable _CRS method when EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is
configured, even without EC sync IRQ support.
Previously, the _CRS method was only generated if EC_ENABLE_SYNC_IRQ or
EC_ENABLE_SYNC_IRQ_GPIO was defined, causing LPC generic memory range
configuration to be skipped on boards that don't use EC sync IRQ which
will results in no communication between kernel and EC.
This change ensures LPC memory range resources are properly exposed
in ACPI considering the hardware limitations where the EC sync IRQ GPIO
is not available for boards using LPC_GENERIC_MEMORY_RANGE.
BUG=437459757
TEST=Build and verify EC LPC memory range is configured in ACPI tables
on boards with EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE enabled
by dumping ssdt tables and also verify 'ectool version' cmd.
ectool version
RO version: ojal-0.0.0-2db24f9+
RW version: ojal-0.0.0-2db24f9+
Change-Id: If63dd631029d2756451fad71a5556bc0b23f507d
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89420
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The document is no longer accessible at the original URL.
Change-Id: I9601b3fb9a86796dafd742961d3d130fb735804e
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89463
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainboard family is set based on the baseboard.
TEST=build/boot google/galtic, verify mainboard family set correctly
in SMBIOS.
Change-Id: Ifb5335c7dad43e8a75dd462a121d2eb711c51ccc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89453
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards all use PDM1 for the microphone topology, and so need to
override the baseboard default.
TEST=boot Win11 on omnigul, verify speakers/microphone work with
Coolstar's drivers.
Change-Id: I55a5886fc02a83640392854cd7132aa811dac6f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89454
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for taking the ifdtool platform parameter via the cmd
line, as well as the output directory. Add double quotes around
variables as needed. Add help output describing new parameter options.
TEST=run script against images from skl, adl, and mtl platforms.
Verify no warning from ifdtool that platform is unknown.
Change-Id: I4a27c9876bf639579b791c894b2cbfdae7ab63c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Introduce a Kconfig option EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC for
reading firmware configuration from Unified Firmware and Second-source
Config (UFSC) [1] from EC CBI. As the UFSC already includes both the
32-bit FW_CONFIG and 32-bit SSFC, this option is incompatible with
EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG.
Also check the size of the data read from CBI.
[1] https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/6974727
BUG=b:448300592
TEST=emerge=skywalker coreboot
BRANCH=none
Change-Id: I2f686838d2f7a6f3eec3bd5224f89389340f7471
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89404
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The changes focus on offering power state current thresholds and Thermal
Design Current (TDC) mode settings.
The Ps1Threshold, Ps2Threshold, and Ps3Threshold new fields configure
current thresholds for different power states. This allows for
fine-tuned power management by specifying current thresholds in 1/4 A
increments. These configurations can help optimize performance based on
specific current requirements for different components like IA, GT, and
SA.
The TdcMode parameter configures TDC mode based on the IRMS supported
bit from Mailbox, offering the option between iPL2 and Irms modes.
BUG=b:449662274
Change-Id: I25b6b9d2bf19ade51e39db06298ffaef98a7897e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88043
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors the MMU configuration for the DMA region by moving
the logic from mmu_cmops.c to the common/mmu_operations.c. This
centralization simplifies the code and removes duplication.
The following changes are included:
- Deleted src/soc/mediatek/common/mmu_cmops.c
- Moved DMA region configuration to mtk_mmu_after_dram
- Updated Makefiles to remove references to the deleted file
BRANCH=none
BUG=none
TEST=emerge-kukui coreboot -j && emerge-elm coreboot -j && \
emerge-rauru coreboot -j
Change-Id: I06289afa74248d55fc1eabeef2f6591bc805a8cf
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89411
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The macros being removed are already defined in the soc/memlayout.h.
Remove the duplicated definitions and include the common header instead.
BUG=none
TEST=emerge-asurada coreboot
Change-Id: I38d9ca2310fbc60bb453b9731203ffb0251cb444
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89410
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change refactors `configure_backlight` function to accept a boolean
'enable' parameter. This provides more explicit control over the
backlight state.
BUG=b:319511268,b:319511268
TEST=emerge-rauru coreboot
Change-Id: Ia713dc792186a9a8080fd9d7ee02738fd372f531
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
