Add the support RAM parts for gothrax.
Here is the ram part number list:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H58G56AK6BX069 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
H9JCNNNBK3MLYR-N6E 0 (0000)
H9JCNNNCP3MLYR-N6E 3 (0011)
K3KL8L80CM-MGCT 4 (0100)
BUG=b:463859361
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: Ia43d300e63d22df27d5632d702a404a18442ea75
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90239
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Ramdump is a debug image loaded during a crash to capture memory
contents for post-crash analysis. This patch adds support for
loading this image during the qclib_rerun() sequence.
Key changes:
1) Introduce QC_RAMDUMP_ENABLE Kconfig option to control ramdump image
loading.
2) Add qclib_check_dload_mode() as a weak function that works in
conjunction with the Kconfig check to decide whether the ramdump
image should be loaded.
3) Add new CBFS file entry and table entry definition for ramdump_meta.
4) Re-use "apdp_ramdump_meta" region for ramdump metadata storage.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I42bcd74c3d236a6af49ec4b548bc9cda33bd0825
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90306
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds build rules for packing the APDP image in CBFS.
It also updates the memory layout to include a dedicated region
for APDP metadata storage (4KB at 0x14890000).
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: Ia3093ef6619dd504c829cf6ba6f672f16070f68a
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch introduces a new Kconfig option, QC_APDP_ENABLE, to control
Application Processor Debug Policy (APDP) image loading. When this
option is enabled, the APDP image is loaded during the
qclib_load_and_run() sequence. It also adds a new CBFS file entry and
table entry definition for apdp_meta, along with a memory region symbol
apdp_ramdump_meta for metadata storage.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I8d0847c99a1129359f2c758b7a07b9c022f1c8c8
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90303
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change ensures that the display is always enabled for the Google
Bluey mainboard as firmware splash screen is POR for this device..
This change helps to avoid an additional reset while doing EC sync
operation by payload.
BUG=none
BRANCH=none
TEST=Able to avoid one additional resets during EC SW sync.
Change-Id: If1d8788cbbd72d6bc4397b1b7160e9f4669716db
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The value 0 passed as the reboot_flags argument to
google_chromeec_reboot is now explicitly defined as
EC_REBOOT_FLAG_IMMEDIATE in ec_commands.h.
Update calls to google_chromeec_reboot with EC_REBOOT_COLD to use the
new flag for clarity and to ensure the intended EC-based reboot is
performed.
This change doesn't introduce anything new, so there's no change
in behavior.
Change-Id: I6701c94101c5085cfcc7fbf2e614c4f23d843225
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The current read calibration data flow may cause memory overwrite due to
struct size mismatch, resulting in fast calibration flow failure. Need
to align the struct for storing DRAM calibration data between coreboot
and mtk-dramk repo to prevent memory overwrite.
BUG=b:450724525
TEST=Bootup ok.
Change-Id: Ic59bc9c7f12c454702ba894dea5dce94984e2121
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90354
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: jason-ch chen <Jason-ch.Chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On AMD non-car system the bootblock is integrated into PSP directories
and copied to host DRAM before reset vector. coreboot knows the exact
DRAM range where the bootblock will be copied to based on
CONFIG_ROMSTAGE_ADDR and CONFIG_C_ENV_BOOTBLOCK_SIZE. The code only
needs to check the exact coreboot program size using linker symbols
measure the right memory range.
Based on the Apollo Lake tspi_soc_measure_bootblock, create an
equivalent implementation for AMD platforms using mem_region_device.
TEST=Bootblock is measured properly on Gigabyte MZ33-AR1 when measured
boot is enabled and CRTM initialization no longer fails.
Change-Id: I163e6b0ef0313e7dbb66ba5b07c35724a14276aa
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89145
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
More complex systems, such as servers, may have scarse space below 4G
for MMIO. With multiple root bridges needing some 32bit MMIO space it
becomes very hard to squeeze all resources. Allow to set 64bit ECAM
MMCONF base address in the MSR to free some space in the 32bit address
space. Of course using 64bit ECAM MMCONF requires the use of x86_64
mode and a proper amount of address space to be mapped with page
tables.
TEST=Set ECAM MMCONF to 0x3ffb00000000 on Gigabyte MZ33-AR1 and observe
the PCI access works in the console output.
Change-Id: I80e5a1bed33e12aa089355df64cc29887acc27f2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89112
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The breaks for `if` and `else` are inconsistent; remove all breaks for
these.
Change-Id: Ie76f38387fd5ef330b432c0462cb1101571c73db
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90286
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The existing brightness level fallback logic duplicated the default
backlight value by hardcoding BRLV to 100% (0x64). This caused divergence
whenever a platform defined a different default brightness through BRIG[0].
This change removes the duplicated default and replaces it with a cached
brightness mechanism using BRVA (valid flag) and BRLV (cached level).
The firmware now:
- Caches the last brightness level exposed to the OS.
- Uses the cached level during early boot/resume when the OpRegion
(BCLM/BCLV) is not yet initialized.
- Falls back to BRIG[0] only when no cached brightness exists.
- Preserves the existing replay-detection logic to keep firmware and OS
brightness state aligned once the graphics driver is active.
This ensures consistent brightness reporting, avoids incorrect 0% fallback
values, and respects board-specific BRIG defaults.
No functional changes occur once the graphics driver has initialized the
OpRegion; the improvement only affects early boot/resume behavior and
eliminates duplicated platform policy.
Change-Id: I651dfd30aa0c283b4e0659e5d19051e1b58204fe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
If the Top Swap mechanism is enabled, after running the bootblock from
the TOP_SWAP region, boot from an updatable COREBOOT_TS FMAP region.
Having flashed the TOP_SWAP bootblock and COREBOOT_TS, this allows the
user to boot a newer version of the firmware with the ability to
revert to the previous known-good version by performing a CMOS reset.
Requires having a read-write COREBOOT_TS region in the FMAP file.
This is part of an ongoing implementation of a redundancy feature
proposed on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
TEST=Boot Protectli VP6650, setting the attempt_slot_b flag to
different values, observing the "Booting from COREBOOT/COREBOOT_TS
region" prints correspondingly.
Change-Id: Ieadc9bfbe940cbec79eb84f16a5d622bfbb82ede
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
To minimize code duplication when adding the new "optiplex_5040" port
CB:88735, the "optiplex_3050" should be turned into a variant first.
Naming of the template inspired by "ifdtool --platform quirk" and recent
"sklkbl_thinkpads" commit. However it's naming is not limmited to its
CPU support since some Coffee Lake (Refresh) CPUs are already tested!
Currently chose a more common name "desktops" although yet only Dell
OptiPlex units are supported Inspiron, Vostro or even Precision desktops
running the same chipset(s) and code should be foreseen.
Open to any other naming / convention suggestions?
Patch stages:
patch1: add variant template with duplicated code some specialized files
but full devicetree.cb as overridetree.cb wont build as variant!
patch2: edit Kconfig(.name) and Makefile.mk to include both variants
trim each overridetree.cb specific & derive common devicetree.cb
builds both variants only tested and verified "optiplex_5040"
patch3: remove "optiplex_5040" variant so this only turns into a variant
containing the converted "optiplex_3050"
patch12 customized gpio between 3050 and 5040 use gpio.c vs gpio.h
Further patches mostly rebasing.
TEST=Checksum BUILD_TIMELESS=1 matches if original build adds 1 ramstage
linked file to variant folder! See comments howto verify checksum.
Change-Id: I16e3b92104f515b334afaacfed740a3b71f5b048
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88726
Reviewed-by: Máté Kukri <km@mkukri.xyz>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for Pantherlake LPCAMM T3 Reference Validation Platform:
- Define PTLP_LPCAMM_T3_RVP board ID (0x02)
- Add memory configuration for LPCAMM including DQ/DQS mapping
- Configure SPD information for LPCAMM modules using SMBus address 0x50
across all channels with MEM_TOPO_LP5_CAMM topology to enable SPD
detection
BUG=none
TEST=Boot LPCAMM T3 RVP and verify memory detection.
Change-Id: I17325241c105a5af5a97931be5c75a025b2bd7c8
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90139
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extend memory initialization to support LPCAMM (Low Profile Compression
Attached Memory Module) configurations:
- Increase DIMM_MAX from default to 16 to accommodate LPCAMM SPD
addressing requirements
- Generalize fill_dimm_module_info() to work with both DDR5 DIMMs and
LP5X LPCAMM modules by using mb_cfg->type instead of hardcoded
MEM_TYPE_DDR5
- Add LPCAMM SPD reading support for MEM_TYPE_LP5X when topology is
MEM_TOPO_LP5_CAMM
- Move DQ/DQS initialization to appropriate locations for each memory
type. LPCAMM modules use LPDDR5X memory technology but require SPD
reading via SMBus similar to traditional DIMMs, unlike typical LP5X
memory-down configurations.
BUG=none
TEST=Build test on Pantherlake platforms with LPCAMM support.
Change-Id: I22743305aa7f93968ec2959de9eaf19b9719260a
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90138
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add MEM_TOPO_LP5_CAMM topology type to support Low Profile Compression
Attached Memory Module (LPCAMM) configurations. LPCAMM is a removable
memory module format that provides similar functionality to DIMMs but
in a different physical form factor. Update the SPD reading logic to
handle both traditional DIMM modules and LPCAMM modules, as both are
removable memory types that require SPD detection and initialization.
This change enables platforms to properly detect and initialize LPCAMM
memory configurations alongside existing DIMM and memory-down support.
BUG=none
TEST=Build test on Intel platforms
Change-Id: I6db2fd76300dd4c96212427d9283b078ca621ed9
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".
Change-Id: I26b8bc194d9f28c2274b87f429821028120a4fcb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90293
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".
Change-Id: I71dcab53b8d570c1a3f37c11ce0b0fb3d86a5d45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90294
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".
Change-Id: Iadc2c7d44d8e89f9b4a8f4adad4ac3dd07466984
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90289
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Start from next stage, Caboc route SSD to PEG60 and change SSD CLK_SRC
CLK_OUT, SSD_CLKREQ(GPP_D8-SRCCLKREQ3#) to port 3.
This CL updates PEG60 CLK_SRC, CLK_OUT to port 3, sets NF1 to GPP_D8-
SRCCLKREQ3. Update fingerprint PCH_FP_BOOT0 to GPP_D5.
Remove PEG62 settings include vGPIO, set NC GPP_H23 (SRCCLKREQ5#),
set NC GPP_F20 (EN_PP3300_SSD) follow schematic 1128A.
BUG=b:464243569, b:45604227, b:441591974
TEST=emerge-brox coreboot
Change-Id: I4376b6532b412215e39be499806e7ebd2eac9841
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Create the ocicat variant of ocelot reference board by copying the
template files to a new directory named for the variant.
Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.
BUG=b:457879750
TEST=util/abuild/abuild -p none -t google/ocelot -x -a
make sure the build includes GOOGLE_OCICAT
Change-Id: I5112703146761ed5902737ba6ec5f9d7889b9cf4
Signed-off-by: chou.pierce <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
According to doc#836031, GPP_V3 defaults to Native F1 with the integrated pull-up enabled. However, coreboot was configuring this pin with the internal pull-up set to NONE, which disabled the pull-up and caused GPP_V3/PWRBTN# to read low, leading to unexpected shutdowns.
Update the pad configuration to use the internal pull-up.
BUG=b:463193164
TEST=boots normally and no unexpected shutdown occurs.
Change-Id: Ia650aa9b60d7ce634827330954b1a9c9ac3d7567
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90218
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Wildcat Lake Ocelot mainboard is missing the
EC_GOOGLE_CHROMEEC_SKUID configuration option, causing the sku_id()
function to call the weak implementation that returns
UNDEFINED_STRAPPING_ID instead of calling
google_chromeec_get_board_sku(). This results in incorrect SKU ID
reporting in the coreboot table.
This patch adds missing EC_GOOGLE_CHROMEEC_SKUID configuration to
retrieve SKU information from the Chrome EC.
BUG=b:459266759
TEST= SKU ID is properly configured as 1
Change-Id: I143bdffe40303336d66d1a42e97872aebcb817a3
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom, Poornima <poornima.tom@intel.com>
Reviewed-by: P, Usha <usha.p@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Move common display mode parameter calculation from SoC-specific
mtk_ddp_mode_set functions to a new common mtk_ddp_mode_set function in
src/soc/mediatek/common/display.c.
Rename the SoC-specific mtk_ddp_mode_set functions to
mtk_ddp_soc_mode_set and modify them to directly accept the calculated
display parameters (format, bits per pixel, width, height, and vertical
refresh rate). This centralizes the common logic and improves code
reusability.
TEST=emerge-rauru coreboot -j && emerge-geralt coreboot -j
Change-Id: I2f86dd609f8ea5225ff4d788206c7494164b6e4b
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN has to be handled differently at
variant level in upcoming mainboards. This patch moves the switch from
upper mc_ehl level to board-specific level.
TEST=Compared .config files for all boards after defconfig completed
before and after the patch for all boards.
Change-Id: I5adb978152eb9f465e30988f39d1ea7815403ce0
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is the MCH Strap Length, and FMSBA is the corresponding
Flash MCH Strap Base Address. See ICH8 datasheet, FLMAP2.
Change-Id: I322c13d9228800a2736b0288377495287521712c
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89614
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Vboot configuration (Kconfig and FMDs for RO only and RW_A layouts).
TEST=Build with UEFIPayload and boot to payload. Verify in cbmem logs
that verstage has executed and selected Slot A in the case of RW_A
layout.
Change-Id: Ide2a3a4b59be5b27bf7315690520c9392a98d044
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Modify the power limit setting like below
PL1 : 15
PL2 : 35
PL4 : 150
BUG=b:464422702
TEST=Build and check the system could boot to OS
Change-Id: I629af9bdf41cd2344d8b4189f49a0e27f5db695d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90246
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
renoir uses the A/B recovery flash layout without the ISH structure. But
this is handled by amdfwtool.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If9d53bf8fb5fe80779af20ccf7aa3bd9d88a5cc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since the structs are the same, we may as well use the ones directly
from the driver (since it implements the standard anyway).
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I44116e5e977029c37e1bf9b9d8ce8d6c022b5b0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The EFI variable store driver (efivars.c) and option backend
(option.c) require EDK2 headers which are x86-specific and not
available in ARM verstage. Use 'all_x86-' instead of 'all-' to
exclude verstage while keeping other x86 stages and SMM.
TEST=build google/dewatt with CFR enabled
Change-Id: I6d0955423cb55658725dfa3025b2118736f5e63b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90296
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Verstage cannot use the UEFI variable store because it runs before
the SMMSTORE is initialized/available, and because the required EDK2
headers are x86-specific. Provide inline stub that returns fallback
values to satisfy console_init() dependency.
TEST=build google/dewatt with CFR enabled
Change-Id: Icaa493692006cf3e0bb194ee3fdd9caf2f51cda1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The OS replays _BCM requests while the graphics driver is
still reinitializing, so hardware brightness can diverge
from what we cached in BRLV. Reapply the cached level once
the OpRegion is ready to keep firmware and OS state aligned.
Change-Id: I2e6ed0936b2e74f55a2c760e7f4fcf56a2e02c53
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Our 18-entry BRIG table advertised is only a handful of steps and
identical AC/DC defaults, so after S3, the OS falls back to the
default index if the the cached entry doesn't match.
Populate BRIG with the full 0–100 ladder so every cached index
corresponds to an actual entry.
Change-Id: I319cf3a0ced3bf6021f9e768f0e9bb5529b12ed5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cache the brightness level requested via _BCM and return it from XBQC
while the IGD OpRegion registers are still zeroed during S3 resume.
Once BCLM is valid we refresh the cache with the hardware reading.
This keeps _BQC from reporting zero after resume.
Change-Id: I3f06c9cf6529da6d634d7b0368f0c88b468f0c45
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add support to reserve 33 MB DRAM memory for display in memlayout.ld
file.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Basic device boot functionality with the specified memory reservation
has been validated. Display functionality has not yet been tested, as
the display driver porting is yet to be done.
Change-Id: I49a4a20b9869bc5cf0b11f4eb6cff7865bb2e761
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90242
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The panel id is sampled with AUXADC_VIN3 (PANEL_ID_HIGH_CHANNEL)
and AUXADC_VIN4 (PANEL_ID_LOW_CHANNEL).
[DEBUG] ADC[2]: Raw value=1744 ID=7
[DEBUG] ADC[3]: Raw value=283 ID=1
[DEBUG] Panel ID: 0x9
BUG=b:448281461
TEST=build and check the CBFS include the panel ID
BRANCH=none
Change-Id: I3b010162bb5b892d528c74e2d38e624465fa90dc
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90190
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Many boards were incorrectly using the VCM I2C address (0x0C) as the
SSDB vcm_type field value. These are two separate fields:
- ssdb.vcm_type: Enum identifying the VCM chip model (VCM_DW9714,
VCM_DW9808, etc.) used by drivers to select appropriate VCM functions
- vcm_address: I2C address of the VCM device (typically 0x0C)
Replace hardcoded "0x0C" values in ssdb.vcm_type with the correct enum
values based on the actual VCM device:
- VCM_DW9714 for boards using DW9714 VCMs
- VCM_DW9808 for boards using DW9768 VCMs (DW9768 doesn't have an enum,
but DW9808 has compatible register layout)
Add vcm_address = "0x0C" to all affected boards to properly specify
the I2C address separately from the VCM type.
This ensures the Windows and Linux camera drivers receive the correct
VCM type information needed for proper initialization and function
pointer selection.
TEST=tested with rest of patch train
Change-Id: I53a560b0b03a1fe49d35ad8238679cc130327ade
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <ericllai@google.com>
The SSDB platform field was unset on many boards, causing the driver
to default to PLAT_SKC (Skylake). This field is required for proper
camera sensor initialization and is validated by the driver.
Set the correct platform enum value based on the SoC.
TEST=tested with rest of patch train
Change-Id: I34e0aba0ba34dabcf25287ff04bc4251135ca09e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90196
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Remove the (unused) disable_ssdb_defaults field and its usage. SSDB
defaults should always be applied to ensure proper camera sensor
configuration. This simplifies the code and ensures consistent behavior
across all camera sensor configurations.
TEST=tested with rest of patch train
Change-Id: I3bc00cdd28ace925b44712a17dec07f7f2b8c97a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Set SSDB version and card type default values, as both fields
are required by both Linux and Windows MIPI camera drivers.
TEST=tested with rest of patch train
Change-Id: Ia43bc61caef427a86883a6295af1606eac00229f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Remove the use_pld and disable_pld_defaults flags and always generate
the Physical Location Descriptor (PLD) for camera sensor devices. PLD
is required for proper camera enumeration and identification in modern
ACPI implementations, so making it optional was incorrect.
Changes:
- Remove use_pld field: PLD generation is now always enabled
- Remove disable_pld_defaults field: PLD defaults are always applied
- Always call apply_pld_defaults() and acpigen_write_pld()
TEST=tested with rest of patch train
Change-Id: Ifd408f32a4feaf9728913dd150d1cb3e7b1c3c60
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add comments for the tail of `struct intel_ssdb`, naming the camera
position, voltage rail, PPR, flash, PHY, lane, and external MCLK fields
instead of treating them as an opaque reserved block. Keeps the struct
aligned with the ACPI blob while making each byte’s meaning explicit.
Change-Id: Id9ae2bf77e901ef0f88b6f51985b59d41c5529d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Switch the `sensor_card_sku` field in `struct intel_ssdb` from a raw
byte to the new `sensor_sku_info` bitfield wrapper so callers can access
the vendor/card type flags symbolically. Field size stays the same, so
layout and behavior are unchanged.
Change-Id: I85ecbbec1a749c07e4d83d953d47d76854447cb1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
