mb/ocelot/var/ocicat: Create ocicat variant
Create the ocicat variant of ocelot reference board by copying the template files to a new directory named for the variant. Due to new_variant.py limitation that repo can no longer be used in inside, created this CL manually following google suggestion. BUG=b:457879750 TEST=util/abuild/abuild -p none -t google/ocelot -x -a make sure the build includes GOOGLE_OCICAT Change-Id: I5112703146761ed5902737ba6ec5f9d7889b9cf4 Signed-off-by: chou.pierce <chou.pierce@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Bob Moragues <moragues@google.com>
This commit is contained in:
chou.pierce
Matt DeVillier
parent
2975d7220a
commit
85101704ae
13 changed files with 1173 additions and 2 deletions
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@ -29,7 +29,7 @@ config BOARD_GOOGLE_OCELOT_COMMON
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select GOOGLE_SMBIOS_MAINBOARD_VERSION
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_SPD_IN_CBFS if !BOARD_GOOGLE_MODEL_KODKOD
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select HAVE_SPD_IN_CBFS if !BOARD_GOOGLE_MODEL_KODKOD && !BOARD_GOOGLE_MODEL_OCICAT
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select I2C_TPM
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_DISABLE_STAGE_CACHE
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@ -51,7 +51,7 @@ config BOARD_GOOGLE_BASEBOARD_OCELOT
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select DRIVERS_INTEL_USB4_RETIMER
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select HAVE_SLP_S0_GATE
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select MAINBOARD_HAS_CHROMEOS
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select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_MODEL_KODKOD
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select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_MODEL_KODKOD && !BOARD_GOOGLE_MODEL_OCICAT
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_IOE_DIE_SUPPORT
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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@ -94,6 +94,16 @@ config BOARD_GOOGLE_MODEL_OJAL
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select EC_GOOGLE_CHROMEEC_RTK
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select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
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config BOARD_GOOGLE_MODEL_OCICAT
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def_bool n
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select BOARD_GOOGLE_BASEBOARD_OCELOT
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select DRIVERS_GENERIC_BAYHUB_LV2
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select DRIVERS_GENERIC_MAX98357A
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select DRIVERS_INTEL_TOUCH
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select FSP_UGOP_EARLY_SIGN_OF_LIFE
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select SPD_CACHE_ENABLE
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select SPD_CACHE_IN_FMAP
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config BOARD_GOOGLE_KODKOD
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select BOARD_GOOGLE_MODEL_KODKOD
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@ -123,6 +133,9 @@ config BOARD_GOOGLE_OCELOTMCHP4ES
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config BOARD_GOOGLE_OJAL
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select BOARD_GOOGLE_MODEL_OJAL
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config BOARD_GOOGLE_OCICAT
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select BOARD_GOOGLE_MODEL_OCICAT
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if BOARD_GOOGLE_OCELOT_COMMON
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config BASEBOARD_DIR
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@ -160,6 +173,7 @@ config DRIVER_TPM_I2C_BUS
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default 0x01 if BOARD_GOOGLE_MODEL_MATSU
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default 0x01 if BOARD_GOOGLE_MODEL_OCELOT
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default 0x01 if BOARD_GOOGLE_MODEL_OJAL
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default 0x01 if BOARD_GOOGLE_MODEL_OCICAT
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config HAVE_SLP_S0_GATE
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def_bool n
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@ -176,6 +190,7 @@ config MAINBOARD_PART_NUMBER
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default "Matsu" if BOARD_GOOGLE_MODEL_MATSU
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default "Ocelot" if BOARD_GOOGLE_MODEL_OCELOT
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default "Ojal" if BOARD_GOOGLE_OJAL
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default "Ocicat" if BOARD_GOOGLE_OCICAT
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config MEMORY_SOLDERDOWN
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def_bool n
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@ -188,6 +203,7 @@ config TPM_TIS_ACPI_INTERRUPT
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default 78 if BOARD_GOOGLE_MODEL_MATSU # GPE0_DW2_14 (GPP_E14)
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default 49 if BOARD_GOOGLE_MODEL_OCELOT # GPE0_DW1_17 (GPP_B17)
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default 49 if BOARD_GOOGLE_MODEL_OJAL # GPE0_DW1_17 (GPP_B17)
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default 49 if BOARD_GOOGLE_MODEL_OCICAT # GPE0_DW1_17 (GPP_B17)
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config UART_FOR_CONSOLE
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int
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@ -202,6 +218,7 @@ config VARIANT_DIR
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default "matsu" if BOARD_GOOGLE_MODEL_MATSU
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default "ocelot" if BOARD_GOOGLE_MODEL_OCELOT
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default "ojal" if BOARD_GOOGLE_MODEL_OJAL
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default "ocicat" if BOARD_GOOGLE_MODEL_OCICAT
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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@ -28,3 +28,6 @@ config BOARD_GOOGLE_OCELOTITE4ES
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config BOARD_GOOGLE_OCELOTMCHP4ES
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bool "-> Ocelotmchp4ES"
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config BOARD_GOOGLE_OCICAT
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bool "-> Ocicat"
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@ -22,6 +22,8 @@
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#define EC_SYNC_IRQ GPP_E08_IRQ
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#elif CONFIG(BOARD_GOOGLE_MODEL_MATSU)
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#define EC_SYNC_IRQ GPP_E08_IRQ
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#elif CONFIG(BOARD_GOOGLE_MODEL_OCICAT)
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#define EC_SYNC_IRQ GPP_E08_IRQ
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#endif
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#define GPIO_PCH_WP GPP_D02
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#define GPIO_SLP_S0_GATE GPP_C08
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11
src/mainboard/google/ocelot/variants/ocicat/Makefile.mk
Normal file
11
src/mainboard/google/ocelot/variants/ocicat/Makefile.mk
Normal file
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@ -0,0 +1,11 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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romstage-y += memory.c
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romstage-$(CONFIG_FW_CONFIG) += fw_config.c
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romstage-$(CONFIG_CHROMEOS_DRAM_PART_NUMBER_IN_CBI) += part_num_to_dram_id.c
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ramstage-y += gpio.c
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romstage-$(CONFIG_FW_CONFIG) += variant.c
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ramstage-$(CONFIG_FW_CONFIG) += variant.c
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ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
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28
src/mainboard/google/ocelot/variants/ocicat/fw_config.c
Normal file
28
src/mainboard/google/ocelot/variants/ocicat/fw_config.c
Normal file
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@ -0,0 +1,28 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/variants.h>
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#include <console/console.h>
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#include <fw_config.h>
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#include <gpio.h>
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#include <inttypes.h>
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/* t: base table; o: override table */
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#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o))
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/* t: table */
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#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
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void fw_config_configure_pre_mem_gpio(void)
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{
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if (!fw_config_is_provisioned()) {
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printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
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return;
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}
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}
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void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
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{
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if (!fw_config_is_provisioned()) {
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printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n");
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return;
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}
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}
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425
src/mainboard/google/ocelot/variants/ocicat/gpio.c
Normal file
425
src/mainboard/google/ocelot/variants/ocicat/gpio.c
Normal file
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@ -0,0 +1,425 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <boardid.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage*/
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static const struct pad_config gpio_table[] = {
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/* GPP_A */
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/* GPP_A00: ESPI_IO0_AIC */
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/* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
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/* GPP_A01: ESPI_IO1_AIC */
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/* GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
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/* GPP_A02: ESPI_IO2_AIC */
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/* GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
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/* GPP_A03: ESPI_IO3_AIC */
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/* GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
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/* GPP_A04: ESPI_CS0_AIC_N */
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/* GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
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/* GPP_A05: ESPI_CLK_AIC */
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/* GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
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/* GPP_A06: ESPI_RST_AIC_N */
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/* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
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/* GPP_A08: M2_GEN4_SSD_RESET_N */
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PAD_CFG_GPO(GPP_A08, 1, PLTRST),
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/* GPP_A09: NC */
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PAD_NC(GPP_A09, NONE),
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/* GPP_A10: NC */
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PAD_NC(GPP_A10, NONE),
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/* GPP_A11: WLAN_RST_N */
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PAD_CFG_GPO(GPP_A11, 1, PLTRST),
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/* GPP_A12: NC */
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PAD_NC(GPP_A12, NONE),
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/* GPP_A13: NC */
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PAD_NC(GPP_A13, NONE),
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/* GPP_A15: NC */
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PAD_NC(GPP_A15, NONE),
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/* GPP_B */
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/* GPP_B00: USBC_SML_CLK_PD */
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PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
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/* GPP_B01: USBC_SML_DATA_PD */
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PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
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/* GPP_B02: NC */
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PAD_NC(GPP_B02, NONE),
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/* GPP_B03: NC */
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PAD_NC(GPP_B03, NONE),
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/* GPP_B04: NC */
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PAD_NC(GPP_B04, NONE),
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/* GPP_B05: EC_ISH_INT_ODL */
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PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
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/* GPP_B06: NC */
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PAD_NC(GPP_B06, NONE),
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/* GPP_B07: NC */
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PAD_NC(GPP_B07, NONE),
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/* GPP_B08: NC */
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PAD_NC(GPP_B08, NONE),
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/* GPP_B09: BT_RF_KILL_N */
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PAD_CFG_GPO(GPP_B09, 1, DEEP),
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/* GPP_B10: NC */
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PAD_NC(GPP_B10, NONE),
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/* GPP_B12: PM_SLP_S0_N */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* GPP_B13: PLT_RST_N */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* GPP_B14: GPP_B14_DDSP_HPDB */
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
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/* GPP_B15: NC */
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PAD_NC(GPP_B15, NONE),
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/* GPP_B16: NC */
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PAD_NC(GPP_B16, NONE),
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/* GPP_B17: NC */
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PAD_NC(GPP_B17, NONE),
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/* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
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/* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
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/* GPP_B20: NC */
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PAD_NC(GPP_B20, NONE),
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/* GPP_B21: NC */
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PAD_NC(GPP_B21, NONE),
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/* GPP_B22: ISH_GP_5_SNSR_HDR */
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PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
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/* GPP_B23: NC */
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PAD_NC(GPP_B23, NONE),
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/* GPP_B24: NC */
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PAD_NC(GPP_B24, NONE),
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/* GPP_B25: NC */
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PAD_NC(GPP_B25, NONE),
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/* GPP_C */
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/* GPP_C00: SPD_SMB_CLK */
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PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
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/* GPP_C01: SPD_SMB_DATA */
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PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
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/* GPP_C02: NC */
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PAD_NC(GPP_C02, NONE),
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/* GPP_C03: NC */
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PAD_NC(GPP_C03, NONE),
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/* GPP_C04: NC */
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PAD_NC(GPP_C04, NONE),
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/* GPP_C05: NC */
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PAD_NC(GPP_C05, NONE),
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/* GPP_C06: NC */
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PAD_NC(GPP_C06, NONE),
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/* GPP_C07: NC */
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PAD_NC(GPP_C07, NONE),
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/* GPP_C08: PM_SLP_S0_N_GPP_CNTRL */
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PAD_CFG_GPO(GPP_C08, 1, PLTRST),
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/* GPP_C09: CLKREQ0_X1_GEN4_M2_WLAN_N */
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PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
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/* GPP_C10: WIFI_RF_KILL_N */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* GPP_C11: NC */
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PAD_NC(GPP_C11, NONE),
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/* GPP_C12: CLKREQ3_X4_GEN4_M2_SSD_N */
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
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/* GPP_C13: NC */
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PAD_NC(GPP_C13, NONE),
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/* GPP_C14: NC */
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PAD_NC(GPP_C14, NONE),
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/* GPP_C15: NC */
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PAD_NC(GPP_C15, NONE),
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/* GPP_C16: NC */
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PAD_NC(GPP_C16, NONE),
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/* GPP_C17: NC */
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PAD_NC(GPP_C17, NONE),
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/* GPP_C18: NC */
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PAD_NC(GPP_C18, NONE),
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/* GPP_C19: NC */
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PAD_NC(GPP_C19, NONE),
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/* GPP_C22: DDPB_HDMI_CTRLCLK */
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PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
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/* GPP_C23: DDPB_HDMI_CTRLDATA */
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PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
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/* GPP_D */
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/* GPP_D01: NC */
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PAD_NC(GPP_D01, NONE),
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/* GPP_D02: SOC_WP_OD */
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PAD_CFG_GPI(GPP_D02, NONE, DEEP),
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/* GPP_D03: NC */
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PAD_NC(GPP_D03, NONE),
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/* GPP_D05: ISH_UART0_ECAIC_RXD */
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PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
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/* GPP_D06: ISH_UART0_ECAIC_TXD */
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PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
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/* GPP_D07: NC */
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PAD_NC(GPP_D07, NONE),
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/* GPP_D08: NC */
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PAD_NC(GPP_D08, NONE),
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/* GPP_D09: NC */
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PAD_NC(GPP_D09, NONE),
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/* GPP_D10: HDA_BCLK_I2S0_SCLK */
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PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
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/* GPP_D11: HDA_SYNC_I2S0_SFRM*/
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PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
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/* GPP_D12: HDA_SDO_I2S0_TXD_STRAP */
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PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
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/* GPP_D13: HDA_HP_SDI0_R */
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PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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/* GPP_D16: NC */
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PAD_NC(GPP_D16, NONE),
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/* GPP_D17: NC */
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PAD_NC(GPP_D17, NONE),
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/* GPP_D19: TCHSCR_REPORT_EN */
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PAD_CFG_GPO(GPP_D19, 1, PLTRST),
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/* GPP_D21: GPP_D21_UFS_REFCLK_R */
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PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
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/* GPP_E */
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/* GPP_E01: NC */
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PAD_NC(GPP_E01, NONE),
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/* GPP_E02: SOC_VR_ALERT_ODL */
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PAD_CFG_NF(GPP_E02, NONE, DEEP, NF2),
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/* GPP_E03: NC */
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PAD_NC(GPP_E03, NONE),
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/* GPP_E05: NC */
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PAD_NC(GPP_E05, NONE),
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/* GPP_E06: NC */
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PAD_NC(GPP_E06, NONE),
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/* GPP_E07: LAN_PCIE_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW_LOCK(GPP_E07, NONE, EDGE_SINGLE, LOCK_CONFIG),
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/* GPP_E08: EC_SOC_INT_ODL */
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PAD_CFG_GPI_APIC_LOCK(GPP_E08, NONE, LEVEL, INVERT, LOCK_CONFIG),
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/* GPP_E09: USB_FP_CONN_1_CONN_2_OC0_N */
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PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
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/* GPP_E10: NC */
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PAD_NC(GPP_E10, NONE),
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/* GPP_E11: NC */
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PAD_NC(GPP_E11, NONE),
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/* GPP_E12: I2C_TCHPAD_SCL */
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PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
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/* GPP_E13: I2C_TCHPAD_SDA */
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
|
||||
/* GPP_E14: GSC_SOC_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_E14, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* GPP_E15: NC */
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
/* GPP_E16: NC */
|
||||
PAD_NC(GPP_E16, NONE),
|
||||
/* GPP_E17: NC */
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
|
||||
/* GPP_E19: NC */
|
||||
PAD_NC(GPP_E19, NONE),
|
||||
/* GPP_E20: NC */
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
/* GPP_E21: I2C_PMC_PD_INT_N */
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
|
||||
/* GPP_E22: NC */
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
|
||||
/* GPP_F */
|
||||
/* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
|
||||
/* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
|
||||
/* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
|
||||
/* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
|
||||
/* GPP_F04: CNV_RF_RESET_R_N */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
|
||||
/* GPP_F05: CRF_CLKREQ_R */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
|
||||
/* GPP_F06: NC */
|
||||
PAD_NC(GPP_F06, NONE),
|
||||
/* GPP_F07: NC */
|
||||
PAD_NC(GPP_F07, NONE),
|
||||
/* GPP_F08: TCH_PNL1_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_F08, 1, PLTRST),
|
||||
/* GPP_F09: M2_UFS_RST_N */
|
||||
PAD_CFG_GPO(GPP_F09, 1, DEEP),
|
||||
/* GPP_F10: ISH_ACCEL_MB_INT_L */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF8),
|
||||
/* GPP_F11: NC */
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
/* GPP_F12: THC_I2C1_SCL_TCH_PAD */
|
||||
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
|
||||
/* GPP_F13: THC_I2C1_SDA_TCH_PAD */
|
||||
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
|
||||
/* GPP_F14: NC */
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
/* GPP_F15: NC */
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
/* GPP_F16: TCHSCR_RST_ODL */
|
||||
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF3),
|
||||
/* GPP_F17: NC */
|
||||
PAD_NC(GPP_F17, NONE),
|
||||
/* GPP_F18: TCHSCR_INT_ODL */
|
||||
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3),
|
||||
/* GPP_F19: NC */
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
/* GPP_F20: CSE_EARLY_SW */
|
||||
PAD_CFG_GPI(GPP_F20, NONE, DEEP),
|
||||
/* GPP_F22: NC */
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
/* GPP_F23: NC */
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
|
||||
/* GPP_H */
|
||||
/* GPP_H00: NC */
|
||||
PAD_NC(GPP_H00, NONE),
|
||||
/* GPP_H01: NC */
|
||||
PAD_NC(GPP_H01, NONE),
|
||||
/* GPP_H02: NC */
|
||||
PAD_NC(GPP_H02, NONE),
|
||||
/* GPP_H03: NC */
|
||||
PAD_NC(GPP_H03, NONE),
|
||||
/* GPP_H04: NC */
|
||||
PAD_NC(GPP_H04, NONE),
|
||||
/* GPP_H05: NC */
|
||||
PAD_NC(GPP_H05, NONE),
|
||||
/* GPP_H06: NC */
|
||||
PAD_NC(GPP_H06, NONE),
|
||||
/* GPP_H07: NC */
|
||||
PAD_NC(GPP_H07, NONE),
|
||||
/* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */
|
||||
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
|
||||
/* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */
|
||||
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
|
||||
/* GPP_H10: NC */
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
/* GPP_H11: NC */
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
/* GPP_H13: CPU_C10_GATE_N_R */
|
||||
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
|
||||
/* GPP_H14: NC */
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
/* GPP_H15: NC */
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
/* GPP_H17: NC */
|
||||
PAD_NC(GPP_H17, NONE),
|
||||
/* GPP_H18: GEN4_SSD_PWREN */
|
||||
PAD_CFG_GPO(GPP_H18, 1, DEEP),
|
||||
/* GPP_H19: NC */
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
/* GPP_H20: NC */
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
/* GPP_H21: I2C1_SDA_TTK_CHROME */
|
||||
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
|
||||
/* GPP_H22: I2C1_SCL_TTK_CHROME */
|
||||
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
|
||||
/* GPP_H23: NC */
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
/* GPP_H24: NC */
|
||||
PAD_NC(GPP_H24, NONE),
|
||||
|
||||
/* GPP_S */
|
||||
/* GPP_S00: NC */
|
||||
PAD_NC(GPP_S00, NONE),
|
||||
/* GPP_S01: NC */
|
||||
PAD_NC(GPP_S01, NONE),
|
||||
/* GPP_S02: NC */
|
||||
PAD_NC(GPP_S02, NONE),
|
||||
/* GPP_S03: NC */
|
||||
PAD_NC(GPP_S03, NONE),
|
||||
/* GPP_S04: DMIC_CLK_A0 */
|
||||
PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
|
||||
/* GPP_S05: DMIC_DATA_0 */
|
||||
PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
|
||||
/* GPP_S06: NC */
|
||||
PAD_NC(GPP_S06, NONE),
|
||||
/* GPP_S07: NC */
|
||||
PAD_NC(GPP_S07, NONE),
|
||||
|
||||
/* GPP_V */
|
||||
/* GPP_V00: PM_BATLOW_N */
|
||||
PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
|
||||
/* GPP_V01: BC_ACOK_MCP */
|
||||
PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
|
||||
/* GPP_V02: LANWAKE_N_R */
|
||||
PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
|
||||
/* GPP_V03: PWRBTN_MCP_N */
|
||||
PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
|
||||
/* GPP_V04: PM_SLP_S3_N */
|
||||
PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
|
||||
/* GPP_V05: PM_SLP_S4_N */
|
||||
PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
|
||||
/* GPP_V06: PM_SLP_A_N */
|
||||
PAD_NC(GPP_V06, NONE),
|
||||
/* GPP_V07: M.2_BTWIFI_SUS_CLK_LS */
|
||||
PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
|
||||
/* GPP_V08: NC */
|
||||
PAD_NC(GPP_V08, NONE),
|
||||
/* GPP_V09: PM_SLP_S5_N */
|
||||
PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
|
||||
/* GPP_V10: NC */
|
||||
PAD_NC(GPP_V10, NONE),
|
||||
/* GPP_V11: NC */
|
||||
PAD_NC(GPP_V11, NONE),
|
||||
/* GPP_V12: WAKE_N */
|
||||
PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
|
||||
/* GPP_V13: NC */
|
||||
PAD_NC(GPP_V13, NONE),
|
||||
/* GPP_V14: NC */
|
||||
PAD_NC(GPP_V14, NONE),
|
||||
/* GPP_V15: NC */
|
||||
PAD_NC(GPP_V15, NONE),
|
||||
/* GPP_V16: GPP_V16_VCCST_EN */
|
||||
PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* GPP_E14: GSC_SOC_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_E14, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */
|
||||
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
|
||||
/* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */
|
||||
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
|
||||
/* GPP_H21: I2C1_SDA_TTK_CHROME */
|
||||
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
|
||||
/* GPP_H22: I2C1_SCL_TTK_CHROME */
|
||||
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
/* Pad configuration in romstage */
|
||||
static const struct pad_config romstage_gpio_table[] = {
|
||||
/* GPP_C00: SPD_SMB_CLK */
|
||||
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
|
||||
/* GPP_C01: SPD_SMB_DATA */
|
||||
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
|
||||
/* GPP_C15: FPS_RST_N */
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
/* Create the stub for romstage gpio, typically use for power sequence */
|
||||
const struct pad_config *variant_romstage_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(romstage_gpio_table);
|
||||
return romstage_gpio_table;
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
|
||||
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
|
||||
};
|
||||
|
||||
DECLARE_CROS_GPIOS(cros_gpios);
|
||||
126
src/mainboard/google/ocelot/variants/ocicat/hda_verb.c
Normal file
126
src/mainboard/google/ocelot/variants/ocicat/hda_verb.c
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */
|
||||
0x10ec12ac, /* Subsystem ID */
|
||||
0x00000013, /* Number of jacks (NID entries) */
|
||||
|
||||
AZALIA_RESET(0x1),
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table */
|
||||
AZALIA_SUBVENDOR(0, 0x10ec12ac),
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
/*
|
||||
* DMIC
|
||||
* Requirement is to use PCH DMIC. Hence,
|
||||
* commented out codec's Internal DMIC.
|
||||
* AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
|
||||
* AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
*/
|
||||
/* Pin widget 0x14 - Front (Port-D) */
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
/* Pin widget 0x18 - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
|
||||
/* Pin widget 0x19 - MIC2 (Port-F) */
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
|
||||
/* Pin widget 0x1A - LINE1 (Port-C) */
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
|
||||
/* Pin widget 0x1B - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
|
||||
/* Pin widget 0x1D - BEEP-IN */
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
|
||||
/* Pin widget 0x1E - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
|
||||
/* Pin widget 0x21 - HP1-OUT (Port-I) */
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
|
||||
/*
|
||||
* Widget node 0x20 - 1
|
||||
* Codec hidden reset and speaker power 2W/4ohm
|
||||
*/
|
||||
0x0205001A,
|
||||
0x0204C003,
|
||||
0x02050038,
|
||||
0x02047901,
|
||||
/*
|
||||
* Widget node 0x20 - 2
|
||||
* Class D power on Reset
|
||||
*/
|
||||
0x0205003C,
|
||||
0x02040354,
|
||||
0x0205003C,
|
||||
0x02040314,
|
||||
/*
|
||||
* Widget node 0x20 - 3
|
||||
* Disable AGC and set AGC limit to -1.5dB
|
||||
*/
|
||||
0x02050016,
|
||||
0x02040C50,
|
||||
0x02050012,
|
||||
0x0204EBC1,
|
||||
/*
|
||||
* Widget node 0x20 - 4
|
||||
* Set AGC Post gain +1.5dB then Enable AGC
|
||||
*/
|
||||
0x02050013,
|
||||
0x02044023,
|
||||
0x02050016,
|
||||
0x02040E50,
|
||||
/*
|
||||
* Widget node 0x20 - 5
|
||||
* Silence detector enabling + Set EAPD to verb control
|
||||
*/
|
||||
0x02050037,
|
||||
0x0204FE15,
|
||||
0x02050010,
|
||||
0x02040020,
|
||||
/*
|
||||
* Widget node 0x20 - 6
|
||||
* Silence data mode Threshold (-90dB)
|
||||
*/
|
||||
0x02050030,
|
||||
0x0204A000,
|
||||
0x0205001B,
|
||||
0x02040A4B,
|
||||
/*
|
||||
* Widget node 0x20 - 7
|
||||
* Default setting-1
|
||||
*/
|
||||
0x05750003,
|
||||
0x05740DA3,
|
||||
0x02050046,
|
||||
0x02040004,
|
||||
/*
|
||||
* Widget node 0x20 - 8
|
||||
* support 1 pin detect two port
|
||||
*/
|
||||
0x02050009,
|
||||
0x0204E003,
|
||||
0x0205000A,
|
||||
0x02047770,
|
||||
/*
|
||||
* Widget node 0x20 - 9
|
||||
* To set LDO1/LDO2 as default
|
||||
*/
|
||||
0x02050008,
|
||||
0x02046A0C,
|
||||
0x02050008,
|
||||
0x02046A0C,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
/* Dos beep path - 1 */
|
||||
0x01470C00,
|
||||
0x02050036,
|
||||
0x02047151,
|
||||
0x01470740,
|
||||
/* Dos beep path - 2 */
|
||||
0x0143b000,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef MAINBOARD_EC_H
|
||||
#define MAINBOARD_EC_H
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
#endif /* MAINBOARD_GPIO_H */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __MAINBOARD_GPIO_H__
|
||||
#define __MAINBOARD_GPIO_H__
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
|
||||
#define GPE_EC_WAKE GPE0_LAN_WAK
|
||||
|
||||
#endif /* __MAINBOARD_GPIO_H__ */
|
||||
36
src/mainboard/google/ocelot/variants/ocicat/memory.c
Normal file
36
src/mainboard/google/ocelot/variants/ocicat/memory.c
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <boardid.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
#define SMBUS_ADDR_DIMM 0x50
|
||||
|
||||
static const struct mb_cfg ddr5_mem_config = {
|
||||
.type = MEM_TYPE_DDR5,
|
||||
|
||||
.ect = true, /* Early Command Training */
|
||||
|
||||
.user_bd = BOARD_TYPE_ULT_ULX,
|
||||
|
||||
.ddr_config = {
|
||||
.dq_pins_interleaved = false,
|
||||
},
|
||||
|
||||
.rcomp = {
|
||||
.resistor = 100,
|
||||
},
|
||||
};
|
||||
|
||||
const struct mb_cfg *variant_memory_params(void)
|
||||
{
|
||||
return &ddr5_mem_config;
|
||||
}
|
||||
|
||||
void variant_get_spd_info(struct mem_spd *spd_info)
|
||||
{
|
||||
spd_info->topo = MEM_TOPO_DIMM_MODULE;
|
||||
spd_info->smbus[0].addr_dimm[0] = SMBUS_ADDR_DIMM;
|
||||
spd_info->smbus[1].addr_dimm[0] = SMBUS_ADDR_DIMM;
|
||||
}
|
||||
421
src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
Normal file
421
src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
Normal file
|
|
@ -0,0 +1,421 @@
|
|||
fw_config
|
||||
field STORAGE 13 14
|
||||
option STORAGE_UNKNOWN 0
|
||||
option STORAGE_NVME_GEN4 1
|
||||
option STORAGE_UFS 2
|
||||
end
|
||||
end
|
||||
|
||||
chip soc/intel/pantherlake
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port - TAP1 Vertical CONN
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # UFC
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 1
|
||||
|
||||
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Type-C Port 1 (Virtual OC)
|
||||
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Type-C Port 2 (Virtual OC)
|
||||
|
||||
register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
|
||||
register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN"
|
||||
|
||||
# Enable EDP in PortA & HDMI in Port B
|
||||
register "ddi_port_A_config" = "1"
|
||||
register "ddi_port_B_config" = "1"
|
||||
register "ddi_ports_config" = "{
|
||||
[DDI_PORT_A] = DDI_ENABLE_HPD,
|
||||
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
|
||||
}"
|
||||
|
||||
register "serial_io_i2c_mode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
register "serial_io_gspi_mode" = "{
|
||||
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| I2C1 | TPM(cr50) |
|
||||
#| I2C4 | Touchpad |
|
||||
#| I2C5 | TouchScreen |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
/* Render OEM footer logo 100px above from the edge */
|
||||
.logo_bottom_margin = 100,
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
.i2c[1] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.early_init = 1,
|
||||
},
|
||||
.i2c[4] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[5] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device ref igpu on
|
||||
chip drivers/gfx/generic
|
||||
register "device_count" = "4"
|
||||
# DDIA for eDP
|
||||
register "device[0].name" = ""LCD0""
|
||||
register "device[0].type" = "panel"
|
||||
# DDIB for HDMI
|
||||
# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
|
||||
register "device[1].name" = ""DD01""
|
||||
# TCP0 (DP-1) for port C0
|
||||
register "device[2].name" = ""DD02""
|
||||
register "device[2].use_pld" = "true"
|
||||
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
# TCP1 (DP-2) for port C1
|
||||
register "device[3].name" = ""DD03""
|
||||
register "device[3].use_pld" = "true"
|
||||
register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device ref dtt on
|
||||
chip drivers/intel/dptf
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""DDR_SOC""
|
||||
register "options.tsr[1].desc" = ""Ambient""
|
||||
register "options.tsr[2].desc" = ""Charger""
|
||||
register "options.tsr[3].desc" = ""wwan""
|
||||
|
||||
## Active Policy
|
||||
# FIXME: below values are initial reference values only
|
||||
register "policies.active" = "{
|
||||
[0] = {
|
||||
.target = DPTF_TEMP_SENSOR_0,
|
||||
.thresholds = {
|
||||
TEMP_PCT(70, 97),
|
||||
TEMP_PCT(65, 90),
|
||||
TEMP_PCT(60, 80),
|
||||
TEMP_PCT(55, 75),
|
||||
TEMP_PCT(50, 65),
|
||||
TEMP_PCT(45, 45),
|
||||
TEMP_PCT(43, 30),
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.target = DPTF_TEMP_SENSOR_1,
|
||||
.thresholds = {
|
||||
TEMP_PCT(70, 97),
|
||||
TEMP_PCT(65, 90),
|
||||
TEMP_PCT(60, 80),
|
||||
TEMP_PCT(55, 75),
|
||||
TEMP_PCT(50, 65),
|
||||
TEMP_PCT(45, 45),
|
||||
TEMP_PCT(43, 30),
|
||||
}
|
||||
},
|
||||
[2] = {
|
||||
.target = DPTF_TEMP_SENSOR_2,
|
||||
.thresholds = {
|
||||
TEMP_PCT(75, 90),
|
||||
TEMP_PCT(70, 80),
|
||||
TEMP_PCT(65, 70),
|
||||
TEMP_PCT(60, 50),
|
||||
}
|
||||
},
|
||||
[3] = {
|
||||
.target = DPTF_TEMP_SENSOR_3,
|
||||
.thresholds = {
|
||||
TEMP_PCT(75, 90),
|
||||
TEMP_PCT(70, 80),
|
||||
TEMP_PCT(65, 70),
|
||||
TEMP_PCT(60, 60),
|
||||
TEMP_PCT(55, 50),
|
||||
TEMP_PCT(50, 40),
|
||||
TEMP_PCT(45, 30),
|
||||
}
|
||||
}
|
||||
}"
|
||||
|
||||
## Passive Policy
|
||||
# TODO: below values are initial reference values only
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000),
|
||||
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000),
|
||||
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
|
||||
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000),
|
||||
}"
|
||||
|
||||
## Critical Policy
|
||||
# TODO: below values are initial reference values only
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
|
||||
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
|
||||
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
|
||||
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
|
||||
}"
|
||||
|
||||
## Power Limits Control
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 25000,
|
||||
.max_power = 25000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 200,
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 95000,
|
||||
.max_power = 95000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 1000,
|
||||
}
|
||||
}"
|
||||
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 3000 },
|
||||
[1] = { 24, 1500 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
|
||||
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||
register "controls.fan_perf" = "{
|
||||
[0] = { 90, 6700, 220, 2200, },
|
||||
[1] = { 80, 5800, 180, 1800, },
|
||||
[2] = { 70, 5000, 145, 1450, },
|
||||
[3] = { 60, 4900, 115, 1150, },
|
||||
[4] = { 50, 3838, 90, 900, },
|
||||
[5] = { 40, 2904, 55, 550, },
|
||||
[6] = { 30, 2337, 30, 300, },
|
||||
[7] = { 20, 1608, 15, 150, },
|
||||
[8] = { 10, 800, 10, 100, },
|
||||
[9] = { 0, 0, 0, 50, }
|
||||
}"
|
||||
|
||||
## Fan options
|
||||
register "options.fan.fine_grained_control" = "true"
|
||||
register "options.fan.step_size" = "2"
|
||||
|
||||
device generic 0 alias dptf_policy on end
|
||||
end
|
||||
end
|
||||
|
||||
device ref iaa off end
|
||||
|
||||
device ref thc0 on
|
||||
register "thc_wake_on_touch[0]" = "true"
|
||||
# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
|
||||
chip drivers/intel/touch
|
||||
register "name" = "INTEL_THC0_NAME"
|
||||
register "mode" = "THC_HID_I2C_MODE"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
|
||||
register "enable_delay_ms" = "2"
|
||||
register "enable_off_delay_ms" = "2"
|
||||
register "wake_on_touch" = "true"
|
||||
# NOTE: Use GpioInt() in _CRS and does not use GPE.
|
||||
register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
|
||||
register "active_ltr" = "1"
|
||||
register "idle_ltr" = "0"
|
||||
register "connected_device" = "TH_SENSOR_ELAN"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device generic 0 alias touch_0_i2c_elan on end
|
||||
end
|
||||
end
|
||||
device ref thc1 on
|
||||
register "thc_wake_on_touch[1]" = "true"
|
||||
chip drivers/intel/touch
|
||||
register "name" = "INTEL_THC1_NAME"
|
||||
register "mode" = "THC_HID_I2C_MODE"
|
||||
register "wake_on_touch" = "true"
|
||||
# NOTE: Use GpioInt() in _CRS and does not use GPE.
|
||||
register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)"
|
||||
register "active_ltr" = "1"
|
||||
register "idle_ltr" = "0"
|
||||
register "connected_device" = "TH_SENSOR_HYNITRON"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device generic 0 alias touch_1_i2c_hynitron on end
|
||||
end
|
||||
end
|
||||
|
||||
device ref tbt_pcie_rp0 on end
|
||||
device ref tbt_pcie_rp1 on end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 2)"
|
||||
device ref tcss_usb3_port0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C1""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
device ref ish on
|
||||
chip drivers/intel/ish
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device ref xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C1""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device ref usb2_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port 1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(3, 1)"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Camera""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
|
||||
device ref usb2_port8 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port 1""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
device ref ufs on
|
||||
probe STORAGE STORAGE_UFS
|
||||
probe STORAGE STORAGE_UNKNOWN
|
||||
end
|
||||
|
||||
device ref pcie_rp1 on
|
||||
probe STORAGE STORAGE_NVME_GEN4
|
||||
probe STORAGE STORAGE_UNKNOWN
|
||||
register "pcie_rp[PCIE_RP(1)]" = "{
|
||||
.clk_src = 3,
|
||||
.clk_req = 3,
|
||||
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "is_storage" = "true"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
|
||||
register "srcclk_pin" = "3"
|
||||
device generic 0 on end
|
||||
end
|
||||
end # Gen4 M.2 SSD
|
||||
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
register "enable_cnvi_ddr_rfim" = "true"
|
||||
use cnvi_bluetooth as bluetooth_companion
|
||||
device generic 0 on end
|
||||
end
|
||||
end # CNVi
|
||||
|
||||
# NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled.
|
||||
# TPM device is under i2c1. Therefore, i2c0 needs to be enabled anyways.
|
||||
device ref i2c0 on end
|
||||
device ref i2c1 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E14_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end
|
||||
device ref i2c4 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
|
||||
register "wake" = "GPE0_DW2_18"
|
||||
register "detect" = "1"
|
||||
device i2c 15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""SYNA0000""
|
||||
register "generic.cid" = ""ACPI0C50""
|
||||
register "generic.desc" = ""Synaptics Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
|
||||
register "generic.wake" = "GPE0_DW2_18"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 0x2c on end
|
||||
end
|
||||
end # I2C4
|
||||
device ref i2c5 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN9004""
|
||||
register "generic.desc" = ""ELAN Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
|
||||
register "generic.detect" = "1"
|
||||
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
|
||||
register "generic.reset_delay_ms" = "150"
|
||||
register "generic.reset_off_delay_ms" = "2"
|
||||
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
|
||||
register "generic.enable_delay_ms" = "6"
|
||||
register "generic.enable_off_delay_ms" = "1"
|
||||
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
|
||||
register "generic.stop_off_delay_ms" = "2"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "generic.use_gpio_for_status" = "true"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 0x10 on end
|
||||
end
|
||||
end # I2C5
|
||||
|
||||
device ref smbus on end
|
||||
device ref hda on
|
||||
chip drivers/sof
|
||||
register "spkr_tplg" = "max98360a"
|
||||
register "jack_tplg" = "rt5682"
|
||||
register "mic_tplg" = "_2ch_pdm0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
|
||||
struct part_num_spd_index {
|
||||
const char part_num[DIMM_INFO_PART_NUMBER_SIZE];
|
||||
int spd_index;
|
||||
};
|
||||
|
||||
static const struct part_num_spd_index part_number_map[] = {
|
||||
{ "H58G56BK8BX068", 0 },
|
||||
{ "H58G66BK7BX067", 1 },
|
||||
{ "H58G66BK8BX067", 2 },
|
||||
{ "H58GE6AK8BX104", 3 },
|
||||
{ "H58G66CK8BX147", 2 },
|
||||
};
|
||||
|
||||
int variant_memory_sku(void)
|
||||
{
|
||||
int index;
|
||||
size_t num_elements = ARRAY_SIZE(part_number_map);
|
||||
const char *part_num = mainboard_get_dram_part_num();
|
||||
|
||||
if (part_num == NULL)
|
||||
die("No part number in CBI, halting boot.\n");
|
||||
|
||||
for (index = 0; index < num_elements; index++) {
|
||||
if (!strcmp(part_num, part_number_map[index].part_num))
|
||||
/* exact match found */
|
||||
return part_number_map[index].spd_index;
|
||||
}
|
||||
|
||||
/* We didn't find a match for part_num, halt boot */
|
||||
die("No part number found looking for %s, halting boot.\n", part_num);
|
||||
}
|
||||
48
src/mainboard/google/ocelot/variants/ocicat/variant.c
Normal file
48
src/mainboard/google/ocelot/variants/ocicat/variant.c
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <boardid.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <fsp/api.h>
|
||||
#include <fw_config.h>
|
||||
#include <intelblocks/hda.h>
|
||||
#include <sar.h>
|
||||
#include <soc/gpio_soc_defs.h>
|
||||
#include <drivers/intel/touch/chip.h>
|
||||
|
||||
void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
|
||||
|
||||
/* Override FSP-M SaGv frequency and gear for DDR5 boards */
|
||||
m_cfg->SaGvFreq[0] = 3200;
|
||||
m_cfg->SaGvGear[0] = GEAR_4;
|
||||
|
||||
m_cfg->SaGvFreq[1] = 4800;
|
||||
m_cfg->SaGvGear[1] = GEAR_4;
|
||||
|
||||
m_cfg->SaGvFreq[2] = 5600;
|
||||
m_cfg->SaGvGear[2] = GEAR_4;
|
||||
|
||||
m_cfg->SaGvFreq[3] = 6400;
|
||||
m_cfg->SaGvGear[3] = GEAR_4;
|
||||
|
||||
/*
|
||||
* Override FSP-M ChannelToCkdQckMapping to map memory channels
|
||||
* to Clock Driver (CKD) and Query Clock (QCK) signals.
|
||||
*/
|
||||
|
||||
const uint8_t channel_to_ckd_qck[] = { 1, 0, 0, 0,
|
||||
0, 0, 0, 0 };
|
||||
memcpy(m_cfg->ChannelToCkdQckMapping, channel_to_ckd_qck
|
||||
, sizeof(channel_to_ckd_qck));
|
||||
|
||||
/*
|
||||
* Override FSP-M PhyClockToCkdDimm to map PHY clocks
|
||||
* to Clock Driver DIMM connections.
|
||||
*/
|
||||
const uint8_t phy_clock_to_ckd_dimm[] = { 4, 0, 4, 0,
|
||||
0, 0, 0, 0 };
|
||||
memcpy(m_cfg->PhyClockToCkdDimm, phy_clock_to_ckd_dimm,
|
||||
sizeof(phy_clock_to_ckd_dimm));
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue