erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/fatcat/var/ruby: Modify power limit configuration

Browse source 
Modify the power limit setting like below
PL1 : 15
PL2 : 35
PL4 : 150

BUG=b:464422702
TEST=Build and check the system could boot to OS

Change-Id: I629af9bdf41cd2344d8b4189f49a0e27f5db695d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90246
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Luca Lai 2025-11-27 14:35:52 +08:00 • committed by Subrata Banik
commit cbfa28b06e
1 changed files with 4 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

8
src/mainboard/google/fatcat/variants/ruby/overridetree.cb
View file

@ -16,14 +16,14 @@ chip soc/intel/pantherlake
# Apply PTL-U's thermal settings here to avoid thermal issues.
register "power_limits_config[PTL_CORE_1]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 152,
.tdp_pl2_override = 35,
.tdp_pl4 = 150,
}"
register "power_limits_config[PTL_CORE_2]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 152,
.tdp_pl2_override = 35,
.tdp_pl4 = 150,
}"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0