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soc/intel/pantherlake: Add LPCAMM memory support

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Extend memory initialization to support LPCAMM (Low Profile Compression
Attached Memory Module) configurations:
- Increase DIMM_MAX from default to 16 to accommodate LPCAMM SPD
  addressing requirements
- Generalize fill_dimm_module_info() to work with both DDR5 DIMMs and
  LP5X LPCAMM modules by using mb_cfg->type instead of hardcoded
  MEM_TYPE_DDR5
- Add LPCAMM SPD reading support for MEM_TYPE_LP5X when topology is
  MEM_TOPO_LP5_CAMM
- Move DQ/DQS initialization to appropriate locations for each memory
  type. LPCAMM modules use LPDDR5X memory technology but require SPD
  reading via SMBus similar to traditional DIMMs, unlike typical LP5X
  memory-down configurations.

BUG=none
TEST=Build test on Pantherlake platforms with LPCAMM support.

Change-Id: I22743305aa7f93968ec2959de9eaf19b9719260a
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90138
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Bora Guvendik 2025-11-20 12:20:32 -08:00 • committed by Matt DeVillier
commit 58cdf9e668
2 changed files with 14 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/soc/intel/pantherlake/Kconfig
View file

@ -389,6 +389,9 @@ config DIMMS_PER_CHANNEL
int
default 2
config DIMM_MAX
default 16
config MRC_CHANNEL_WIDTH
int
default 16

19
src/soc/intel/pantherlake/meminit.c
View file

@ -167,20 +167,18 @@ static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect);
}
#define DDR5_CH_DIMM_OFFSET(ch, dimm) ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm))
#define CH_DIMM_OFFSET(ch, dimm) ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm))
static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
static void fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
const struct mem_spd *spd_info)
{
for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) {
for (size_t ch = 0; ch < soc_mem_cfg[mb_cfg->type].num_phys_channels; ch++) {
for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch];
mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] =
size_t mrc_ch = soc_mem_cfg[mb_cfg->type].phys_to_mrc_map[ch];
mem_cfg->SpdAddressTable[CH_DIMM_OFFSET(mrc_ch, dimm)] =
spd_info->smbus[ch].addr_dimm[dimm] << 1;
}
}
mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
}
void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
@ -204,12 +202,17 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
* updated to support DDR5 EEPROM reading.
*/
if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
return;
}
break;
case MEM_TYPE_LP5X:
meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config);
/* For LPCAMM, read SPD using SMBus driver */
if (spd_info->topo == MEM_TOPO_LP5_CAMM)
fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
break;
default:
die("Unsupported memory type(%d)\n", mb_cfg->type);