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mb/lenovo/m900_tiny: Enable Vboot

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Add Vboot configuration (Kconfig and FMDs for RO only and RW_A layouts).

TEST=Build with UEFIPayload and boot to payload. Verify in cbmem logs
that verstage has executed and selected Slot A in the case of RW_A
layout.

Change-Id: Ide2a3a4b59be5b27bf7315690520c9392a98d044
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Michał Kopeć 2025-03-29 14:25:11 +01:00 • committed by Matt DeVillier
commit a87e699f04
3 changed files with 77 additions and 0 deletions
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11
src/mainboard/lenovo/m900_tiny/Kconfig
View file

@ -41,4 +41,15 @@ config PRERAM_CBMEM_CONSOLE_SIZE
config DIMM_SPD_SIZE
default 512 #DDR4
config VBOOT
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_FWMP
select GBB_FLAG_DISABLE_LID_SHUTDOWN
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select HAS_RECOVERY_MRC_CACHE
select VBOOT_VBNV_FLASH
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
endif

30
src/mainboard/lenovo/m900_tiny/vboot-ro.fmd Normal file
View file

@ -0,0 +1,30 @@
FLASH 16M {
SI_ALL 8M {
SI_DESC 4K
SI_GBE 8K
SI_ME
}
SI_BIOS 8M {
RW_MISC 2M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
SMMSTORE(PRESERVE) 256K
RW_ELOG(PRESERVE) 16K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
RW_NVRAM(PRESERVE) 24K
}
WP_RO {
FMAP 2K
RO_FRID 128
RO_PADDING 1920
GBB 120K
COREBOOT(CBFS)
}
}
}

36
src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd Normal file
View file

@ -0,0 +1,36 @@
FLASH 16M {
SI_ALL 8M {
SI_DESC 4K
SI_GBE 8K
SI_ME
}
SI_BIOS 8M {
RW_MISC 2M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
SMMSTORE(PRESERVE) 256K
RW_ELOG(PRESERVE) 16K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
RW_NVRAM(PRESERVE) 24K
}
RW_SECTION_A 3M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 128
}
WP_RO 3M {
FMAP 2K
RO_FRID 128
RO_PADDING 1920
GBB 120K
COREBOOT(CBFS)
}
}
}