That means if it ever gets called while CAR is active, our stack will be
dropped and mayhem will ensue.
Besides that, it just replicated stage0.S functionality which already
nukes all MTRRs before enabling CAR.
We could move XIP ROM caching from stage0.S to early_mtrr_init(). It
would probably slow down booting a bit, but the amount of asm code would
be reduced.
Thanks to Corey for telling me that early_mtrr_init() broke booting for
him.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1067 f3766cd6-281f-0410-b1cd-43a5c92072e9
Whether SMM is added or not depends on the mainboard. To enable SMM,
the Kconfig variable SMM should be set, and the SMM variable should be
defined in the mainbard.
Also correct a type CONFIG_HPET should be HPET.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1065 f3766cd6-281f-0410-b1cd-43a5c92072e9
by Stefan.
The only changes left from r1057 are:
- Added comments
- Two initial pushes of 0x00000000 (32 bits each) to the stack as safety
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1058 f3766cd6-281f-0410-b1cd-43a5c92072e9
with a wrong calling convention of stage1_phase1() this caused stage1 to
assume BIST had failed.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1057 f3766cd6-281f-0410-b1cd-43a5c92072e9
the console banner and the option table will never be updated with more
recent build.h strings.
Thanks to Mart Raudsepp for spotting this oddness.
x86emu doesn't care about the contents of build.h, it just uses build.h
to check whether it is compiled in conjunction with coreboot.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1036 f3766cd6-281f-0410-b1cd-43a5c92072e9
It includes an ide option that has to be there, and fixes a CPU test in
Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1021 f3766cd6-281f-0410-b1cd-43a5c92072e9
Index: arch/x86/intel/core2/stage1.c
Initial core2 disable_car and stop_ap
disable_car is wrong but we can fix that tomorrow -- it's core 2 day on friday!
Index: arch/x86/via/stage1.c
Add empty stop_ap()
Index: mainboard/kontron/986lcd-m/stage1_debug.c
Cleanup
Index: mainboard/kontron/986lcd-m/initram.c
Cleanup
Index: mainboard/jetway/j7f2/stage1.c
Remove definition of stop_ap; this belongs in the cpu!
Index: southbridge/intel/i82801gx/libsmbus.c
Fix definition of TIMEOUT (i.e. remove it)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1019 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is a complete rewrite of my earlier stack checker proposal.
It works for CAR and RAM, has better abstraction and actually gives us
nice results.
The stack checker is default off due to its rather measurable impact on
boot speed.
Diagnostic messages are printed on first initialization, directly after
RAM init and directly before passing control to the payload. Sample qemu
log is attached. Extract from that log follows:
coreboot-3.0.986 Fri Nov 7 04:04:37 CET 2008 starting...
(console_loglevel=8)
Initial lowest stack is 0x0008fe98
Choosing fallback boot.
[...]
Done RAM init code
After RAM init, lowest stack is 0x0008fe30
Done printk() buffer move
[...]
LAR: load_file_segments: Failed for normal/payload
Before handoff to payload, lowest stack is 0x0008bf50
FATAL: No usable payload found.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1012 f3766cd6-281f-0410-b1cd-43a5c92072e9
processor to reset. Fix this bug and actually disable CAR.
With this patch v3 has better C7 CAR code than v2 (which skips two key
MTRRs).
Thanks to Corey Osgood for testing countless debug patches.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1010 f3766cd6-281f-0410-b1cd-43a5c92072e9
and keep getting called away ... waiting for 1024 procs takes patience!)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1008 f3766cd6-281f-0410-b1cd-43a5c92072e9
This actually starts to get compile errors, instead of config errors.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@994 f3766cd6-281f-0410-b1cd-43a5c92072e9
obvious that they are needed, so a comment to that effect will hopefully
prevent accidental "cleanups" in the future when nobody remembers the
history of that makefile rule anymore.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@988 f3766cd6-281f-0410-b1cd-43a5c92072e9
workarounds are better than instant reboots, mangle the code so that it
only switches stacks and flushes the cache.
There are two genuine fix in there as well:
We have to switch %esp before CAR is disabled. That way, the stack is
always valid.
And one of the nastier bugs easily happening in C: We had a pointer to a
const struct, but we wanted a const pointer to a struct. This kills the
(correct) warning about that code.
Many thanks to Corey for testing countless iterations of that code.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested and
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@978 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@976 f3766cd6-281f-0410-b1cd-43a5c92072e9
Make cmos.layout work with incomprehensible tool -- just turn off checksums.
Add static.c to list of files covered by kscope
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@975 f3766cd6-281f-0410-b1cd-43a5c92072e9
alue. There
is a known bug in v2/v3 wherein a BAR that is set is ignored. This change will c
ome in very
slowly as it is a bit tricky to get right as we redesign the dev code.
Also make the vm86 stuff use the SRC instead of OBJ names so we can see it in ks
cope.
Finally, beginnings of documentation changes, not finished yet.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@965 f3766cd6-281f-0410-b1cd-43a5c92072e9
CAR disabling operation. Untested, but it should work.
Please note that the code is incomplete, but that should at least not
affect stage2.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@945 f3766cd6-281f-0410-b1cd-43a5c92072e9
expansion ROMs are active.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@940 f3766cd6-281f-0410-b1cd-43a5c92072e9
the reserved regions substracted from them. This patch introduces a check
to weed them out, splitting when necessary
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@937 f3766cd6-281f-0410-b1cd-43a5c92072e9
arch_write_tables(), before a number of routines that write/reserve
stuff are executed (in my test this only affects the 0x0-0x500 region
but I notice there's other stuff too).
Attached patch moves it down, solving the problem. Because stage1 can no
longer assume the MBI is at 0xf0000, I had to add a return path for stage2
to give it a pointer, using its exit status value.
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@936 f3766cd6-281f-0410-b1cd-43a5c92072e9
directory. Look for it there.
Introduce the STAGE0_DYNAMIC_SRC makefile variable to handle this and
other generated stage1 code.
Thanks to Ron for spotting this bug.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@935 f3766cd6-281f-0410-b1cd-43a5c92072e9
at any given moment. The code is generic enough to handle this in a
processor-specific way behind the scenes if needed.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@933 f3766cd6-281f-0410-b1cd-43a5c92072e9
have a CAR area outside the usual RAM area. For those processors, we
have to implement a stack copying and switching mechanism. Since gcc
can't be told that the stack just moved, split stage1_main() into
stage1_phase1() and stage1_phase2() and stage1_phase3().
stage1_phase1() is the new entry point in stage1 and will handle
everything up to the point where we want to disable CAR.
Switching the stack, disabling CAR and handling other tasks related to
the stack switch (printk buffer move) is all wrapped in the
stage1_phase2() function.
stage1_phase2() calls disable_car() which then calls stage1_phase3().
stage1_phase3() is the former second half of stage1_main().
Notes about this patch:
- Code flow is almost unchanged for Qemu, K8 and Geode. No extensive new
testing required.
- We can support stack-keeping and stack-relocating architectures at the
same time, so C7 is definitely supportable
- The comment in stage1_phase2 says "some of this is not yet done". That
refers to the nonexisting code for stack switching on C7.
- "Minimal changes, maximum benefit".
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@932 f3766cd6-281f-0410-b1cd-43a5c92072e9
I did change the /bin/bash to /bin/sh per the comments.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@919 f3766cd6-281f-0410-b1cd-43a5c92072e9
This required lots of preparatory work to not make the existing stage0
situation worse.
Thanks to Jason Zhao we got a skeleton CAR code for VIA C7 based on
older v2 code.
I cleaned it up, modified it to fit into the improved v3 stage0 code
infrastructure and believe this is mostly merge-ready.
Thanks to Bari Ari for getting the code to me for rewrite/review.
Thanks to Corey Osgood who kept me going with helpful early tests and
motivation.
Thanks to everybody who reviewed my code.
CONFIG_CARTEST shall not be enabled (breaks the build).
CONFIG_XIP_ROM_{SIZE,BASE} shall not be set (breaks the build).
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Jason Zhao <jasonzhao@viatech.com.cn>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@915 f3766cd6-281f-0410-b1cd-43a5c92072e9
up correctly on bus 1 --- i.e., the scan of the 8111 bridge works. It
even
tries to find the vga rom to run it, which we did not get before.
the pci bus map built by coreboot matches simnow.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@910 f3766cd6-281f-0410-b1cd-43a5c92072e9
We had a jump instead of a call to stage1_main in geodelx/stage0.S. That
means all accesses to bist and init_detected were off by 8 bytes and
collided with accesses to the global variable pointer.
Found during my cleanup runs.
This bug had the following effects:
1.) If gcc had decided to reload bist from stack after initializing the
global variable pointer, bist would have been nonzero, an indicator for
processor failure.
2.) If gcc had decided to use the stack location of bist as a scratch
register (and it probably is free to do so as long as the contents are
restored before returning), it would have clobbered the global variable
pointer, leading to NULL pointer dereferences.
3.) Any accesses to init_detected would have resulted in accessing 4
bytes above the top of stack (0x87ffc-0x87fff), something the rest of
the code deliberately avoids.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@909 f3766cd6-281f-0410-b1cd-43a5c92072e9
implementations. Factor out the 16 bit code with associated protected
mode activation.
I'm open to moving even more common code out, but this is a well-defined
start.
This cleanup has been prepared for by r902, r905 and r907.
Boot tested on qemu. Build tested on i586, geodelx, k8.
The diffstat is most enlightening:
amd/stage0.S | 145 ---------------------------------------------
geodelx/stage0.S | 145 ---------------------------------------------
i586/stage0.S | 145 ---------------------------------------------
stage0_common.S | 145 +++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 148 insertions(+), 432 deletions(-)
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@908 f3766cd6-281f-0410-b1cd-43a5c92072e9
CAR code.
Reduce the diff of the mostly identical parts to zero. That involves
changing comments, whitespace and instruction order.
Now we can split out the common parts more easily and concentrate on the
differences.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@907 f3766cd6-281f-0410-b1cd-43a5c92072e9
except for the actual CAR code and inital #includes and #defines.
Reduce the diff of the mostly identical parts to zero. That involves
changing comments, whitespace and instruction order to the best variant
present in the 3 files.
Now we can split out the common parts more easily and concentrate on the
differences.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@905 f3766cd6-281f-0410-b1cd-43a5c92072e9
byte-for-byte identical. That makes factoring out easier.
Fix a duplicated BIST save for K8.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@902 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@901 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@900 f3766cd6-281f-0410-b1cd-43a5c92072e9
arch/x86/i586/stage0.S to make it consistent with the other variants of
that code.
Clean up two superfluous rules from arch/x86/Makefile which were needed
before. That makefile change also fixes a latent bug which may have been
exposed by later additions to the tree.
Compile tested on all arches.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@899 f3766cd6-281f-0410-b1cd-43a5c92072e9
- Coding style and whitespace fixes.
- Remove obsolete comments, fix incorrect ones.
- Use the full/canonical name of mainboards/vendors everywhere.
- Update the list of USB Debug capable chipsets from
http://www.coreboot.org/EHCI_Debug_Port.
- s/LB/CB/ for the CONSOLE_PREFIX kconfig option.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@879 f3766cd6-281f-0410-b1cd-43a5c92072e9
