Get via to use standard mtrr init functions. Start to document them.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://coreboot.org/repository/coreboot-v3@976 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-11-01 00:53:01 +00:00
commit 4964e25101
4 changed files with 12 additions and 16 deletions

View file

@ -106,6 +106,10 @@ void do_early_mtrr_init(const unsigned long *mtrr_msrs)
}
/**
* Call this function early in stage1 to enable mtrrs, which will ensure
* caching of ROM
*/
void early_mtrr_init(void)
{
static const unsigned long mtrr_msrs[] = {

View file

@ -30,21 +30,6 @@
#include <mtrr.h>
#include <via_c7.h>
#ifdef NO_IDEA_WHETHER_THIS_IS_RELEVANT_ON_C7
/**
* Set the MTRR for initial ram access.
* be warned, this will be used by core other than core 0/node 0 or core0/node0 when cpu_reset.
* This warning has some significance I don't yet understand.
*/
void set_init_ram_access(void)
{
set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK);
}
#endif
#define __stringify_1(x) #x
#define __stringify(x) __stringify_1(x)
/**
* Disable Cache As RAM (CAR) after memory is setup.
*/

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@ -18,7 +18,9 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
$(src)/arch/x86/stage1_mtrr.c \
$(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/via/cn700/initram.c \

View file

@ -36,10 +36,15 @@ void stop_ap(void)
void hardware_stage1(void)
{
void early_mtrr_init(void);
void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase);
u32 dev;
post_code(POST_START_OF_MAIN);
/* do this or watch the system run slowly */
early_mtrr_init();
vt1211_enable_serial(0x2e, 2, 0x3f8);
/* Enable multifunction for northbridge. */