Minor fixes and improvements for v3, mostly for Kconfig files (trivial).
- Coding style and whitespace fixes. - Remove obsolete comments, fix incorrect ones. - Use the full/canonical name of mainboards/vendors everywhere. - Update the list of USB Debug capable chipsets from http://www.coreboot.org/EHCI_Debug_Port. - s/LB/CB/ for the CONSOLE_PREFIX kconfig option. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@879 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann
parent
42e98f5d49
commit
8e6d45e059
10 changed files with 62 additions and 62 deletions
8
Kconfig
8
Kconfig
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@ -64,7 +64,7 @@ config WHOLE_PROGRAM_COMPILE
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bool "Enable whole-program optimizations (DANGEROUS)"
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depends EXPERT && EXPERIMENTAL
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help
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Enable gcc -fwhole-program -combine for select code.
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Enable 'gcc -fwhole-program -combine' for select code.
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Needs lots of annotation in stage1 and stage2.
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Works for initram only.
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This increases compile time (no parallel compilation possible
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@ -111,8 +111,6 @@ config SUPERIO_FINTEK_F71805F
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config SUPERIO_ITE_IT8716F
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boolean
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# Source all northbridge/southbridge/superio Kconfig files:
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menu "Payload"
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config PAYLOAD_ELF_LOADER
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@ -122,8 +120,8 @@ config PAYLOAD_ELF_LOADER
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This option allows an unparsed ELF paylaod to be added and loaded.
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choice
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prompt "Payload type"
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default PAYLOAD_NONE
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prompt "Payload type"
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default PAYLOAD_NONE
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config PAYLOAD_ELF
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bool "An ELF executable payload file"
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@ -60,62 +60,62 @@ config CONFIG_HPET
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boolean
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depends CPU_AMD_K8
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help
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Whether to configure a High Precision Event Timer. Note that HPETs are
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known to be bug-prone.
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Whether to configure a High Precision Event Timer (HPET). Note that
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HPETs are known to be bug-prone.
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config K8_REV_F_SUPPORT
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hex
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default 0 if CPU_AMD_K8
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help
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Whether to include rev F support
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Whether to include rev F support.
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config K8_SCAN_PCI_BUS
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hex
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default 0 if CPU_AMD_K8
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help
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Whether to scan the PCI bus in stage1
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Whether to scan the PCI bus in stage1.
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config K8_ALLOCATE_IO_RANGE
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hex
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default 0 if CPU_AMD_K8
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help
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Whether to allocate IO space in stage1
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Whether to allocate I/O space in stage1.
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config K8_ALLOCATE_MMIO_RANGE
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hex
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default 0 if CPU_AMD_K8
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help
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Whether to allocate MMIO space in stage1.
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Comment from code:
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Do we need allocate MMIO? Currently we direct
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last 64M to southbridge link (sblink) only,
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We can not lose access to last 4M range to ROM.
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Whether to allocate MMIO space in stage1.
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Comment from code: Do we need allocate MMIO? Currently we direct
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last 64M to southbridge link (sblink) only. We can not lose access
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to last 4M range to ROM.
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config LOGICAL_CPUS
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hex
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depends CPU_AMD_K8
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default 1
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help
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How many logical CPUs there are. Fix me.
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How many logical CPUs there are. FIXME.
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config MAX_PHYSICAL_CPUS
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hex
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depends CPU_AMD_K8
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default 1
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help
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Max number of physical CPUs (sockets)
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Maximum number of physical CPUs (sockets).
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config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
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hex
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default 0 if CPU_AMD_K8
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help
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Config with 4 CPUs even if more are installed
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Config with 4 CPUs even if more are installed.
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config CROSS_BAR_47_56
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hex
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default 0 if CPU_AMD_K8
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help
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Configure for the type of crossbar on the mainboard.
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Configure for the type of crossbar on the mainboard.
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config OPTION_TABLE
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boolean
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@ -128,14 +128,14 @@ config PIRQ_TABLE
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boolean
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help
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This option is used to determine whether the mainboard has
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a PIRQ table, which is the old way to set up interrupt routing.
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a PIRQ table, which is the old way to set up interrupt routing.
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It is usually set in mainboard/*/Kconfig.
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config ACPI_TABLE
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boolean
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help
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This option is used to determine whether the mainboard has
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an ACPI table.
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an ACPI table.
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It is usually set in mainboard/*/Kconfig.
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config SMP
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@ -143,9 +143,8 @@ config SMP
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depends CPU_I586 || CPU_AMD_K8
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default 0
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help
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This option is used to enable certain functions to make
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coreboot work correctly on symmetric multi processor
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systems.
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This option is used to enable certain functions to make coreboot
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work correctly on symmetric multi processor systems.
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It is usually set in mainboard/*/Kconfig.
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config IOAPIC
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@ -153,7 +152,7 @@ config IOAPIC
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depends ARCH_X86 && CPU_AMD_K8
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default 0
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help
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If you want to configure an IOAPIC, set this.
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If you want to configure an IOAPIC, set this.
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config CARBASE
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hex
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@ -177,36 +176,37 @@ config CBMEMK
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default 0x1000 if CPU_AMD_GEODELX
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default 0x2000 if CPU_AMD_K8
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help
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This option sets the top of the memory area, in KiB,
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This option sets the top of the memory area, in KiB,
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used for coreboot.
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config K8_HT_FREQ_1G_SUPPORT
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hex
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default 1 if CPU_AMD_K8
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help
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1 Ghz. support. Opteron E0 or later can support
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1G HT, but still depends on the mainboard
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1 GHz support. Opteron E0 or later can support 1G HT,
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but still depends on the mainboard.
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config HT_FREQ_800MHZ
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hex
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default 1 if CPU_AMD_K8
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help
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Can we run HT at 800 Mhz
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Can we run HT at 800 MHz.
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config USBDEBUG_DIRECT
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boolean
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depends SOUTHBRIDGE_NVIDIA_MCP55
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default 0
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help
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Determines if we enable USB Direct debugging. If you don't have a dongle,
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this is probably of no value to you.
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Determines if we enable USB Direct debugging. If you don't have
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a dongle, this is probably of no value to you.
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config APIC_ID_OFFSET
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hex "APIC ID offset"
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default 0x10
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depends IOAPIC
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help
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This is entirely mainboard dependent. 0x10 is a *typical* setting but not always a good setting.
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This is entirely mainboard dependent. 0x10 is a *typical* setting
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but not always a good setting.
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menu "Debugging"
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@ -214,6 +214,6 @@ config CARTEST
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bool "Test CAR area"
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default n
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help
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Test the CAR area after it has been set up.
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Test the CAR area after it has been set up.
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endmenu
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@ -36,7 +36,6 @@ choice
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execute PCI option ROMs natively (32bit x86 system required),
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in an emulator (x86emu), or ignore option ROM execution.
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config PCI_OPTION_ROM_RUN_X86EMU
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bool "x86emu"
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select PCI_OPTION_ROM_RUN
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@ -47,7 +46,6 @@ config PCI_OPTION_ROM_RUN_X86EMU
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x86emu is slow, big and safe. All 16bit x86 code is executed
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in an encapsulated environment where it can not break out.
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config PCI_OPTION_ROM_RUN_VM86
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bool "vm86"
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select PCI_OPTION_ROM_RUN
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@ -64,7 +62,6 @@ config PCI_OPTION_ROM_RUN_NONE
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bool "Disabled"
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help
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Do not execute PCI option ROMs at all.
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If you choose this option, VGA plugin cards will not be initialized.
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endchoice
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@ -74,7 +71,7 @@ config MULTIPLE_VGA_INIT
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bool "Initialize all VGA cards"
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depends PCI_OPTION_ROM_RUN
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help
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If you enable this option, all VGA cards will be initialized
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If you enable this option, all VGA cards will be initialized.
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If you disable this option, only the first VGA card will be
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initialized.
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@ -82,7 +79,7 @@ config INITIALIZE_ONBOARD_VGA_FIRST
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bool "Initialize onboard VGA first"
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depends PCI_OPTION_ROM_RUN
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help
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Initialize onboard VGA chips before any plugin VGA cards
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Initialize onboard VGA chips before any plugin VGA cards
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are initialized.
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endmenu
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@ -99,17 +96,17 @@ config PCI_64BIT_PREF_MEM
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bool "64 bit prefetchable memory addresses"
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depends CPU_AMD_K8
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help
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Enable support for 64-bit prefetchable memory addresses in PCI.
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Enable support for 64-bit prefetchable memory addresses in PCI.
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config HW_MEM_HOLE_SIZEK
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hex "HW memory hole size in KB"
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depends CPU_AMD_K8
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default 0x1000
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help
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Some chipsets support setting up a "hole" at the top of memory. It is essentially
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a hole torn in the physical address space so that you can fit non-memory resources
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(e.g. flash) at the top of the 4G address space. Given that this only happens on machines
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with lots of memory, the default 4 MB is a very reasonable value.
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Some chipsets support setting up a "hole" at the top of memory.
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It is essentially a hole torn in the physical address space so that
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you can fit non-memory resources (e.g. flash) at the top of the 4G
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address space. Given that this only happens on machines with lots
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of memory, the default 4 MB is a very reasonable value.
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endmenu
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16
lib/Kconfig
16
lib/Kconfig
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@ -200,15 +200,21 @@ config CONSOLE_USB
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Debug Port capability. Controllers which are known to work:
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* 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
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* 10de:0088 NVIDIA MCP2A
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* 10de:005b NVIDIA CK804
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* 10de:036d NVIDIA MCP55
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* 8086:24cd Intel ICH4/ICH4-M
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* 8086:24dd Intel ICH5
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* 8086:265c Intel ICH6
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* 8086:268c Intel 631xESB/632xESB/3100
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* 8086:27cc Intel ICH7
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* 8086:2836 Intel ICH8
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* 8086:283a Intel ICH8
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* 8086:293a Intel ICH9
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* 10de:0088 NVIDIA MCP2A
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* 10de:005b NVIDIA CK804
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* 10de:026e NVIDIA MCP51
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* 10de:036d NVIDIA MCP55
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* 10de:03f2 NVIDIA MCP61
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* 1002:4386 ATI/AMD SB600
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* 1106:3104 VIA VX800
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See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list.
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@ -216,12 +222,12 @@ comment "Cosmetic console options"
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depends EXPERT && (CONSOLE_SERIAL || CONSOLE_USB)
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config CONSOLE_PREFIX
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bool "Prefix all console output with '(LB)'"
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bool "Prefix all console output with '(CB)'"
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depends EXPERT && (CONSOLE_SERIAL || CONSOLE_USB)
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default n
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help
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When you enable this option, coreboot will prefix each line of
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console output with '(LB)'.
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console output with '(CB)'.
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config CONSOLE_BUFFER
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boolean "Console memory buffer support"
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@ -116,7 +116,7 @@ void console_tx_byte(unsigned char byte, void *arg)
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#ifdef CONFIG_CONSOLE_PREFIX
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uart8250_tx_byte(TTYSx_BASE, '\n');
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uart8250_tx_byte(TTYSx_BASE, '(');
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uart8250_tx_byte(TTYSx_BASE, 'L');
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uart8250_tx_byte(TTYSx_BASE, 'C');
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uart8250_tx_byte(TTYSx_BASE, 'B');
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uart8250_tx_byte(TTYSx_BASE, ')');
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uart8250_tx_byte(TTYSx_BASE, ' ');
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@ -40,8 +40,7 @@ config VENDOR_AMD
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config VENDOR_AMP
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bool "AMP"
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help
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Select this option for various systems from
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Advanced Micro Devices, Inc.
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Select this option for various systems from AMP.
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config VENDOR_ARTECGROUP
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bool "Artec Group"
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@ -49,9 +48,9 @@ config VENDOR_ARTECGROUP
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Select this option for various systems from the Artec Group.
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config VENDOR_GIGABYTE
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bool "Gigabyte"
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bool "GIGABYTE"
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help
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Select this option for various systems from Gigabyte
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Select this option for various systems from GIGABYTE.
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config VENDOR_EMULATION
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bool "Emulated systems"
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@ -56,7 +56,7 @@ config BOARD_AMD_SERENGETI
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select SUPERIO_WINBOND_W83627HF
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select IOAPIC
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help
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AMD Serengeti
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AMD Serengeti development board.
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endchoice
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@ -33,7 +33,7 @@ config BOARD_AMP_TINYGX
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select SUPERIO_ITE_IT8716F
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select PIRQ_TABLE
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help
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AMP TinyGX
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AMP TinyGX board.
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endchoice
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@ -24,7 +24,7 @@ choice
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depends on VENDOR_GIGABYTE
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config BOARD_GIGABYTE_M57SLI
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bool "M57SLI"
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bool "GA-M57SLI-S4"
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select ARCH_X86
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select OPTION_TABLE
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select CPU_AMD_K8
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@ -33,7 +33,7 @@ config BOARD_GIGABYTE_M57SLI
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select SUPERIO_ITE_IT8716F
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select IOAPIC
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help
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Gigabyte M57SLI
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GIGABYTE GA-M57SLI-S4.
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endchoice
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@ -24,7 +24,7 @@ choice
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depends on VENDOR_PCENGINES
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config BOARD_PCENGINES_ALIX1C
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bool "ALIX1.C"
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bool "ALIX.1C"
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select ARCH_X86
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select CPU_AMD_GEODELX
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select OPTION_TABLE
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@ -33,7 +33,7 @@ config BOARD_PCENGINES_ALIX1C
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select SUPERIO_WINBOND_W83627HF
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select PIRQ_TABLE
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help
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PC Engines ALIX1.C.
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PC Engines ALIX.1C.
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config BOARD_PCENGINES_ALIX2C3
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bool "ALIX.2C3"
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Loading…
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Reference in a new issue