Add core2 stage1.c dependency
Index: arch/x86/intel/core2/stage1.c Initial core2 disable_car and stop_ap disable_car is wrong but we can fix that tomorrow -- it's core 2 day on friday! Index: arch/x86/via/stage1.c Add empty stop_ap() Index: mainboard/kontron/986lcd-m/stage1_debug.c Cleanup Index: mainboard/kontron/986lcd-m/initram.c Cleanup Index: mainboard/jetway/j7f2/stage1.c Remove definition of stop_ap; this belongs in the cpu! Index: southbridge/intel/i82801gx/libsmbus.c Fix definition of TIMEOUT (i.e. remove it) Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1019 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
321ff1c2f6
commit
5a205b9067
7 changed files with 195 additions and 11 deletions
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@ -125,7 +125,7 @@ ifeq ($(CONFIG_CPU_AMD_K8),y)
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else
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ifeq ($(CONFIG_CPU_INTEL_CORE2),y)
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STAGE0_CAR_OBJ = intel/core2/stage0.o
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#STAGE0_ARCH_X86_SRC += intel/core2/stage1.c
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STAGE0_ARCH_X86_SRC += intel/core2/stage1.c
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else
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ifeq ($(CONFIG_CPU_VIA_C7),y)
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STAGE0_CAR_OBJ = via/stage0.o
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96
arch/x86/intel/core2/stage1.c
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96
arch/x86/intel/core2/stage1.c
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@ -0,0 +1,96 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <msr.h>
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#include <macros.h>
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#include <cpu.h>
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#include <stage1.h>
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#include <globalvars.h>
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#include <string.h>
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#include <mtrr.h>
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/**
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* Disable Cache As RAM (CAR) after memory is setup.
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*/
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void disable_car(void)
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{
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printk(BIOS_DEBUG, "disable_car entry\n");
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/* Determine new global variable location. Stack organization from top
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* Top 4 bytes are reserved
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* Pointer to global variables
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* Global variables
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*
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* Align the result to 8 bytes
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*/
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struct global_vars *const newlocation = (struct global_vars *)((RAM_STACK_BASE - sizeof(struct global_vars *) - sizeof(struct global_vars)) & ~0x7);
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/* Copy global variables to new location. */
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memcpy(newlocation, global_vars(), sizeof(struct global_vars));
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printk(BIOS_DEBUG, "disable_car global_vars copy done\n");
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/* Set the new global variable pointer. */
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*(struct global_vars **)(RAM_STACK_BASE - sizeof(struct global_vars *)) = newlocation;
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printk(BIOS_DEBUG, "disable_car global_vars pointer adjusted\n");
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printk(BIOS_DEBUG, "entering asm code now\n");
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__asm__ __volatile__(
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" movl %[newesp], %%esp \n"
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/* We don't need cache as ram for now on */
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/* disable cache */
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" movl %%cr0, %%eax \n"
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" orl $(0x1<<30),%%eax \n"
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" movl %%eax, %%cr0 \n"
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/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
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/* clear sth */
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" xorl %%eax, %%eax \n"
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" xorl %%edx, %%edx \n"
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" movl $0x201, %%ecx \n"
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" wrmsr \n"
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" movl $0x200, %%ecx \n"
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" wrmsr \n"
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/* Set the default memory type and disable fixed and enable variable MTRRs */
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" movl %[_MTRRdefType_MSR], %%ecx \n"
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" xorl %%edx, %%edx \n"
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/* Enable Variable and Disable Fixed MTRRs */
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" movl $0x00000800, %%eax \n"
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" wrmsr \n"
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/* enable cache */
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" movl %%cr0, %%eax \n"
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" andl $0x9fffffff,%%eax \n"
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" movl %%eax, %%cr0 \n"
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" wbinvd \n"
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" call stage1_phase3 \n"
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:: [newesp] "i" (newlocation),
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[_MTRRdefType_MSR] "i" (MTRRdefType_MSR)
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: "memory");
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}
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void stop_ap(void)
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{
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}
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@ -90,3 +90,8 @@ void disable_car(void)
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[_MTRRdefType_MSR] "i" (MTRRdefType_MSR)
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: "memory");
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}
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void stop_ap(void)
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{
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}
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@ -28,12 +28,6 @@
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#include <superio/fintek/f71805f/f71805f.h>
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#include <northbridge/via/cn700/cn700.h>
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/* Placeholders, build fails without them */
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void stop_ap(void)
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{
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//int noop;
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}
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void hardware_stage1(void)
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{
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u32 dev;
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@ -33,7 +33,6 @@
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#include <string.h>
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#include <msr.h>
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#include <io.h>
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#include <amd/k8/k8.h>
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#include <mc146818rtc.h>
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#include <spd.h>
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@ -73,6 +72,92 @@ u8 spd_read_byte(u16 device, u8 address)
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return do_smbus_read_byte(device, address);
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}
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static void early_ich7_init(void)
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{
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u8 reg8;
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u32 reg32;
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// program secondary mlt XXX byte?
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pci_conf1_write_config8(PCI_BDF(0, 0x1e, 0), 0x1b, 0x20);
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// reset rtc power status
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reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xa4);
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reg8 &= ~(1 << 2);
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pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xa4, reg8);
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// usb transient disconnect
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reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xad);
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reg8 |= (3 << 0);
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pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xad, reg8);
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reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xfc);
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reg32 |= (1 << 29) | (1 << 17);
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pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xfc, reg32);
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reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xdc);
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reg32 |= (1 << 31) | (1 << 27);
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pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xdc, reg32);
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RCBA32(0x0088) = 0x0011d000;
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RCBA16(0x01fc) = 0x060f;
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RCBA32(0x01f4) = 0x86000040;
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RCBA32(0x0214) = 0x10030549;
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RCBA32(0x0218) = 0x00020504;
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RCBA8(0x0220) = 0xc5;
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reg32 = RCBA32(0x3410);
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reg32 |= (1 << 6);
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RCBA32(0x3410) = reg32;
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reg32 = RCBA32(0x3430);
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reg32 &= ~(3 << 0);
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reg32 |= (1 << 0);
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RCBA32(0x3430) = reg32;
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RCBA32(0x3418) |= (1 << 0);
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RCBA16(0x0200) = 0x2008;
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RCBA8(0x2027) = 0x0d;
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RCBA16(0x3e08) |= (1 << 7);
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RCBA16(0x3e48) |= (1 << 7);
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RCBA32(0x3e0e) |= (1 << 7);
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RCBA32(0x3e4e) |= (1 << 7);
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// next step only on ich7m b0 and later:
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reg32 = RCBA32(0x2034);
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reg32 &= ~(0x0f << 16);
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reg32 |= (5 << 16);
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RCBA32(0x2034) = reg32;
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}
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static void rcba_config(void)
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{
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/* Set up virtual channel 0 */
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//RCBA32(0x0014) = 0x80000001;
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//RCBA32(0x001c) = 0x03128010;
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/* Device 1f interrupt pin register */
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RCBA32(0x3100) = 0x00042210;
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/* Device 1d interrupt pin register */
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RCBA32(0x310c) = 0x00214321;
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/* dev irq route register */
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RCBA16(0x3140) = 0x0132;
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RCBA16(0x3142) = 0x3241;
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RCBA16(0x3144) = 0x0237;
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RCBA16(0x3146) = 0x3210;
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RCBA16(0x3148) = 0x3210;
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/* Enable IOAPIC */
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RCBA8(0x31ff) = 0x03;
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/* Enable upper 128bytes of CMOS */
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RCBA32(0x3400) = (1 << 2);
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/* Disable unused devices */
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RCBA32(0x3418) = 0x000e0063;
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/* Enable PCIe Root Port Clock Gate */
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// RCBA32(0x341c) = 0x00000001;
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}
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/**
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* main for initram for the AMD DBM690T
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* @param init_detected Used to indicate that we have been started via init
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@ -89,6 +174,11 @@ u8 spd_read_byte(u16 device, u8 address)
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*/
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int main(void)
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{
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void i945_early_initialization(void);
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void enable_smbus(void);
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int fixup_i945_errata(void);
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void i945_late_initialization(void);
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if (MCHBAR16(SSKPD) == 0xCAFE) {
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printk(BIOS_DEBUG, "soft reset detected.\n");
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boot_mode = 1;
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@ -102,7 +192,7 @@ int main(void)
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/* Enable SPD ROMs and DDR-II DRAM */
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enable_smbus();
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#if DEFAULT_CONSOLE_LOGLEVEL > 8
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#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
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dump_spd_registers();
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#endif
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@ -25,7 +25,6 @@
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#define SMBUS_MEM_DEVICE_START 0x50
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@ -32,8 +32,8 @@
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#include "i82801gx.h"
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/* this is very chipset-specific. */
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#define SMBUS_TIMEOUT (100*1000*10)
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/* These are common functions used in stage 1 and stage2 */
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#warning why do we have an smbus_delay here
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void smbus_delay(void)
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{
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inb(0x80);
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