Carl-Daniel Hailfinger 3bb18f8a3c Add support for Cache-as-RAM on VIA C7 processors in v3. ... This required lots of preparatory work to not make the existing stage0 situation worse. Thanks to Jason Zhao we got a skeleton CAR code for VIA C7 based on older v2 code. I cleaned it up, modified it to fit into the improved v3 stage0 code infrastructure and believe this is mostly merge-ready. Thanks to Bari Ari for getting the code to me for rewrite/review. Thanks to Corey Osgood who kept me going with helpful early tests and motivation. Thanks to everybody who reviewed my code. CONFIG_CARTEST shall not be enabled (breaks the build). CONFIG_XIP_ROM_{SIZE,BASE} shall not be set (breaks the build). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Jason Zhao <jasonzhao@viatech.com.cn> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@915 f3766cd6-281f-0410-b1cd-43a5c92072e9		2008-10-11 00:07:36 +00:00
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x86	Add support for Cache-as-RAM on VIA C7 processors in v3.	2008-10-11 00:07:36 +00:00