stage0 code for GeodeLX, K8 and i586 is mostly identical everywhere
except for the actual CAR code and inital #includes and #defines. Reduce the diff of the mostly identical parts to zero. That involves changing comments, whitespace and instruction order to the best variant present in the 3 files. Now we can split out the common parts more easily and concentrate on the differences. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@905 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Carl-Daniel Hailfinger
parent
a76e76a6e1
commit
ef06e83ef4
3 changed files with 227 additions and 228 deletions
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@ -43,6 +43,7 @@ _stage0:
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/* Save the BIST result. */
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movl %eax, %ebp;
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/* thanks to kmliu@sis.com.tw for this TLB fix */
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/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
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* executing any further code. Even though paging is disabled we
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* could still get false address translations due to the TLB if we
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@ -54,8 +55,8 @@ _stage0:
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/* Switch to protected mode. */
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/* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
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* using BFD version 2.15.94.0.2.2 20041220 this works fine without
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* all the ld hackery and so on. So leave it as is with this comment.
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* using BFD version 2.15.94.0.2.2 20041220 this works fine without all
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* the ld hackery and other things. So leave it as is with this comment.
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*/
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data32 lgdt %cs:gdtptr
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@ -98,7 +99,7 @@ gdt16x:
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt16xend:
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/* From now on we are 32bit. */
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/* From now on we are 32 bit. */
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.code32
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/* We have two gdts where we could have one. That is ok.
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@ -110,7 +111,6 @@ gdt16xend:
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* good descriptor is at offset 8. So you word-align the table, and
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* then because you chose 8, you get a nice 64-bit aligned GDT entry,
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* which is good as this is the size of the entry.
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*
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* Just in case you ever wonder why people do this.
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*/
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.align 4
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@ -147,7 +147,7 @@ gdt_end:
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* Note: Aligned to 4 so that we are sure that the prefetch
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* NOTE: Aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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@ -303,7 +303,7 @@ clear_fixed_var_mtrr_out:
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#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
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#endif
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#if CacheSize > 0x8000
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#if CacheSize > 0x8000
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/* enable caching for 32K-64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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simplemask CacheSize, 0x8000
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@ -36,6 +36,7 @@ _stage0:
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/* Save the BIST result. */
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movl %eax, %ebp;
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/* thanks to kmliu@sis.com.tw for this TLB fix */
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/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
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* executing any further code. Even though paging is disabled we
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* could still get false address translations due to the TLB if we
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@ -47,8 +48,8 @@ _stage0:
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/* Switch to protected mode. */
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/* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
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* using BFD version 2.15.94.0.2.2 20041220 this works fine without
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* all the ld hackery and so on. So leave it as is with this comment.
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* using BFD version 2.15.94.0.2.2 20041220 this works fine without all
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* the ld hackery and other things. So leave it as is with this comment.
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*/
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data32 lgdt %cs:gdtptr
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@ -103,7 +104,6 @@ gdt16xend:
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* good descriptor is at offset 8. So you word-align the table, and
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* then because you chose 8, you get a nice 64-bit aligned GDT entry,
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* which is good as this is the size of the entry.
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*
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* Just in case you ever wonder why people do this.
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*/
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.align 4
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@ -140,7 +140,7 @@ gdt_end:
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* Note: Aligned to 4 so that we are sure that the prefetch
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* NOTE: Aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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@ -37,141 +37,140 @@
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_stage0:
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cli
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/* save the BIST result */
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/* Save the BIST result. */
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movl %eax, %ebp;
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/* thanks to kmliu@sis.com.tw for this TLB fix */
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/* IMMEDIATELY invalidate the translation lookaside buffer before
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* executing any further code. Even though paging is disabled we
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* could still get false address translations due to the TLB if we
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/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
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* executing any further code. Even though paging is disabled we
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* could still get false address translations due to the TLB if we
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* didn't invalidate it.
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*/
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB */
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movl %eax, %cr3 /* Invalidate TLB. */
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/* switch to protected mode */
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/* Switch to protected mode. */
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/* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
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* using BFD version 2.15.94.0.2.2 20041220 this works fine without all
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* the ld hackery and other things. So leave it as is with this comment.
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* the ld hackery and other things. So leave it as is with this comment.
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*/
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data32 lgdt %cs:gdtptr
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* Restore BIST result */
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/* Restore BIST result. */
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movl %ebp, %eax
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// port80_post(0x23)
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// port80_post (0x23) /* post 0x01 */
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/* Now we are in protected mode. Jump to a 32 bit code segment. */
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data32 ljmp $ROM_CODE_SEG, $protected_stage0
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/* I am leaving this weird jump in here in the event that future gas bugs force it to be used. */
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#.byte 0x66
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.code32
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#ljmp $ROM_CODE_SEG, $protected_stage0
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data32 ljmp $ROM_CODE_SEG, $protected_stage0
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#.code16
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.align 4
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/* I am leaving this weird jump in here in the event that future gas
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* bugs force it to be used.
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*/
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/* .byte 0x66 */
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.code32
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/* ljmp $ROM_CODE_SEG, $protected_stage0 */
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/* .code16 */
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.align 4
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.globl gdt16
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gdt16 = . - _stage0
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gdt16 = . - _stage0
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gdt16x:
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.word gdt16xend - gdt16x -1 /* compute the table limit */
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.word gdt16xend - gdt16x -1 /* Compute the table limit. */
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.long gdt16x
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.word 0
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.word 0
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/* selgdt 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x10,flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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/* selgdt 0x10, flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt16xend:
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/* From now on we are 32bit */
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/* From now on we are 32 bit. */
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.code32
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/* We have two gdts where we could have one. That is ok.
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*
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* Let's not worry about this -- optimizing gdt is pointless since we're
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* only in it for a little bit.
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*
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* BTW note the trick below: The GDT points to ITSELF, and the first good
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* descriptor is at offset 8. So you word-align the table, and then because
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* you chose 8, you get a nice 64-bit aligned GDT entry, which is good as
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* this is the size of the entry.
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* Just in case you ever wonder why people do this.
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*/
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.align 4
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/* We have two gdts where we could have one. That is ok.
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*
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* Let's not worry about this -- optimizing gdt is pointless since
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* we're only in it for a little bit.
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*
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* Btw. note the trick below: The GDT points to ITSELF, and the first
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* good descriptor is at offset 8. So you word-align the table, and
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* then because you chose 8, you get a nice 64-bit aligned GDT entry,
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* which is good as this is the size of the entry.
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* Just in case you ever wonder why people do this.
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*/
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.align 4
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.globl gdtptr
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.globl gdt_limit
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gdt_limit = gdt_end - gdt - 1 /* compute the table limit */
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gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */
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gdt:
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gdtptr:
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.word gdt_end - gdt -1 /* compute the table limit */
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.long gdt /* we know the offset */
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.word 0
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.word gdt_end - gdt -1 /* Compute the table limit. */
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.long gdt /* We know the offset. */
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.word 0
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/* selgdt 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x10,flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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/* selgdt 0x10, flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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/* selgdt 0x18, flat code segment for CAR */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x20,flat data segment for CAR */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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/* selgdt 0x20, flat data segment for CAR */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt_end:
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/*
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* When we come here we are in protected mode. We expand
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* the stack and copies the data segment from ROM to the
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* memory.
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*
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* NOTE: Aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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/* When we come here we are in protected mode. We expand the stack
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* and copy the data segment from ROM to the memory.
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*
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* NOTE: Aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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.align 4
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.globl protected_stage0
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protected_stage0:
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//This code was used by v2. TODO
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lgdt %cs:gdtptr
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ljmp $ROM_CODE_SEG, $__protected_stage0
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/* This code was used by v2. TODO. */
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lgdt %cs:gdtptr
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ljmp $ROM_CODE_SEG, $__protected_stage0
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.globl __protected_stage0
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__protected_stage0:
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/* Save the BIST value */
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movl %eax, %ebp
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/* Save the BIST result. */
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movl %eax, %ebp
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port80_post (0x01) /* post 0x01 */
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port80_post(0x01)
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movw $ROM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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movw $ROM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Restore the BIST value to %eax */
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movl %ebp, %eax
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/* Restore the BIST value to %eax. */
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movl %ebp, %eax
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.align 4
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@ -179,9 +178,9 @@ __protected_stage0:
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/* We will use 4Kbytes only for cache as ram. This is
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* enough to fit in our stack.
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*
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*
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* disable HyperThreading is done by eswar
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* the other is very similar to the AMD CAR, except remove amd specific msr
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* the other is very similar to the AMD CAR, except remove amd specific msr
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*/
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#define CacheSize CONFIG_CARSIZE
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@ -195,102 +194,102 @@ __protected_stage0:
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movl %eax, %ebp
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CacheAsRam:
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/* Check whether the processor has HT capability */
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movl $01, %eax
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cpuid
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btl $28, %edx
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jnc NotHtProcessor
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bswapl %ebx
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cmpb $01, %bh
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jbe NotHtProcessor
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/* Check whether the processor has HT capability */
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movl $01, %eax
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cpuid
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btl $28, %edx
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jnc NotHtProcessor
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bswapl %ebx
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cmpb $01, %bh
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jbe NotHtProcessor
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/* It is a HT processor; Send SIPI to the other logical processor
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* within this processor so that the CAR related common system
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/* It is a HT processor; Send SIPI to the other logical processor
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* within this processor so that the CAR related common system
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* registers are programmed accordingly
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*/
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/* Use some register that is common to both logical processors
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* as semaphore. Refer Appendix B, Vol.3
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/* Use some register that is common to both logical processors
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* as semaphore. Refer Appendix B, Vol.3
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*/
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xorl %eax, %eax
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xorl %edx, %edx
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movl $0x250, %ecx
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wrmsr
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xorl %eax, %eax
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xorl %edx, %edx
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movl $0x250, %ecx
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wrmsr
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/* Figure out the logical AP's APIC ID; the following logic will work
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* only for processors with 2 threads.
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/* Figure out the logical AP's APIC ID; the following logic will work
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* only for processors with 2 threads.
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*
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* Refer to Vol 3. Table 7-1 for details about this logic
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* Refer to Vol 3. Table 7-1 for details about this logic
|
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*/
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movl $0xFEE00020, %esi
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movl (%esi), %ebx
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andl $0xFF000000, %ebx
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bswapl %ebx
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btl $0, %ebx
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jnc LogicalAP0
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andb $0xFE, %bl
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jmp SendSIPI
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movl $0xFEE00020, %esi
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movl (%esi), %ebx
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andl $0xFF000000, %ebx
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bswapl %ebx
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btl $0, %ebx
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jnc LogicalAP0
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andb $0xFE, %bl
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jmp SendSIPI
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LogicalAP0:
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orb $0x01, %bl
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orb $0x01, %bl
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SendSIPI:
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bswapl %ebx /* ebx - logical AP's APIC ID */
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bswapl %ebx /* ebx - logical AP's APIC ID */
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/* Fill up the IPI command registers in the Local APIC mapped to
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* default address and issue SIPI to the other logical processor
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/* Fill up the IPI command registers in the Local APIC mapped to
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* default address and issue SIPI to the other logical processor
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* within this processor die.
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*/
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RetrySIPI:
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movl %ebx, %eax
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movl $0xFEE00310, %esi
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movl %eax, (%esi)
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movl %ebx, %eax
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movl $0xFEE00310, %esi
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movl %eax, (%esi)
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/* SIPI vector - F900:0000 */
|
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movl $0x000006F9, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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/* SIPI vector - F900:0000 */
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movl $0x000006F9, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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movl $0x30, %ecx
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movl $0x30, %ecx
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SIPIDelay:
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pause
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decl %ecx
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jnz SIPIDelay
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pause
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decl %ecx
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jnz SIPIDelay
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movl (%esi), %eax
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andl $0x00001000, %eax
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jnz RetrySIPI
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movl (%esi), %eax
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andl $0x00001000, %eax
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jnz RetrySIPI
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/* Wait for the Logical AP to complete initialization */
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/* Wait for the Logical AP to complete initialization */
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LogicalAPSIPINotdone:
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movl $0x250, %ecx
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rdmsr
|
||||
orl %eax, %eax
|
||||
jz LogicalAPSIPINotdone
|
||||
movl $0x250, %ecx
|
||||
rdmsr
|
||||
orl %eax, %eax
|
||||
jz LogicalAPSIPINotdone
|
||||
|
||||
|
||||
|
||||
NotHtProcessor:
|
||||
/* Set the default memory type and enable fixed and variable MTRRs */
|
||||
movl $MTRRdefType_MSR, %ecx
|
||||
xorl %edx, %edx
|
||||
/* Enable Variable and Fixed MTRRs */
|
||||
movl $0x00000c00, %eax
|
||||
wrmsr
|
||||
/* Set the default memory type and enable fixed and variable MTRRs */
|
||||
movl $MTRRdefType_MSR, %ecx
|
||||
xorl %edx, %edx
|
||||
/* Enable Variable and Fixed MTRRs */
|
||||
movl $0x00000c00, %eax
|
||||
wrmsr
|
||||
|
||||
/*Clear all MTRRs */
|
||||
xorl %edx, %edx
|
||||
movl $fixed_mtrr_msr, %esi
|
||||
clear_fixed_var_mtrr:
|
||||
lodsl (%esi), %eax
|
||||
testl %eax, %eax
|
||||
jz clear_fixed_var_mtrr_out
|
||||
lodsl (%esi), %eax
|
||||
testl %eax, %eax
|
||||
jz clear_fixed_var_mtrr_out
|
||||
|
||||
movl %eax, %ecx
|
||||
xorl %eax, %eax
|
||||
wrmsr
|
||||
movl %eax, %ecx
|
||||
xorl %eax, %eax
|
||||
wrmsr
|
||||
|
||||
jmp clear_fixed_var_mtrr
|
||||
jmp clear_fixed_var_mtrr
|
||||
clear_fixed_var_mtrr_out:
|
||||
|
||||
/* 0x06 is the WB IO type for a given 4k segment.
|
||||
|
|
@ -336,92 +335,92 @@ clear_fixed_var_mtrr_out:
|
|||
#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
|
||||
#endif
|
||||
|
||||
#if CacheSize > 0x8000
|
||||
/* enable caching for 32K-64K using fixed mtrr */
|
||||
movl $0x268, %ecx /* fix4k_c0000*/
|
||||
#if CacheSize > 0x8000
|
||||
/* enable caching for 32K-64K using fixed mtrr */
|
||||
movl $0x268, %ecx /* fix4k_c0000*/
|
||||
simplemask CacheSize, 0x8000
|
||||
wrmsr
|
||||
wrmsr
|
||||
#endif
|
||||
|
||||
/* enable caching for 0-32K using fixed mtrr */
|
||||
movl $0x269, %ecx /* fix4k_c8000*/
|
||||
/* enable caching for 0-32K using fixed mtrr */
|
||||
movl $0x269, %ecx /* fix4k_c8000*/
|
||||
simplemask CacheSize, 0
|
||||
wrmsr
|
||||
|
||||
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
|
||||
/* enable write base caching so we can do execute in place
|
||||
* on the flash rom.
|
||||
*/
|
||||
movl $0x202, %ecx
|
||||
xorl %edx, %edx
|
||||
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
|
||||
wrmsr
|
||||
/* enable write base caching so we can do execute in place
|
||||
* on the flash rom.
|
||||
*/
|
||||
movl $0x202, %ecx
|
||||
xorl %edx, %edx
|
||||
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
|
||||
wrmsr
|
||||
|
||||
movl $0x203, %ecx
|
||||
movl $0x0000000f, %edx
|
||||
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
|
||||
wrmsr
|
||||
movl $0x203, %ecx
|
||||
movl $0x0000000f, %edx
|
||||
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
|
||||
wrmsr
|
||||
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
|
||||
|
||||
/* enable cache */
|
||||
movl %cr0, %eax
|
||||
andl $0x9fffffff,%eax
|
||||
movl %eax, %cr0
|
||||
/* enable cache */
|
||||
movl %cr0, %eax
|
||||
andl $0x9fffffff,%eax
|
||||
movl %eax, %cr0
|
||||
|
||||
/* Read the range with lodsl*/
|
||||
movl $CacheBase, %esi
|
||||
movl $CacheBase, %esi
|
||||
cld
|
||||
movl $(CacheSize>>2), %ecx
|
||||
rep lodsl
|
||||
movl $(CacheSize>>2), %ecx
|
||||
rep lodsl
|
||||
|
||||
/* Clear the range */
|
||||
movl $CacheBase, %edi
|
||||
movl $(CacheSize>>2), %ecx
|
||||
xorl %eax, %eax
|
||||
rep stosl
|
||||
movl $CacheBase, %edi
|
||||
movl $(CacheSize>>2), %ecx
|
||||
xorl %eax, %eax
|
||||
rep stosl
|
||||
|
||||
|
||||
/* TODO: make this a config variable */
|
||||
#if CONFIG_CARTEST
|
||||
/* check the cache as ram */
|
||||
movl $CacheBase, %esi
|
||||
movl $(CacheSize>>2), %ecx
|
||||
.xin1:
|
||||
movl %esi, %eax
|
||||
movl %eax, (%esi)
|
||||
decl %ecx
|
||||
je .xout1
|
||||
add $4, %esi
|
||||
jmp .xin1
|
||||
.xout1:
|
||||
movl $CacheBase, %esi
|
||||
movl $(CacheSize>>2), %ecx
|
||||
.xin1:
|
||||
movl %esi, %eax
|
||||
movl %eax, (%esi)
|
||||
decl %ecx
|
||||
je .xout1
|
||||
add $4, %esi
|
||||
jmp .xin1
|
||||
.xout1:
|
||||
|
||||
movl $CacheBase, %esi
|
||||
movl $CacheBase, %esi
|
||||
// movl $(CacheSize>>2), %ecx
|
||||
movl $4, %ecx
|
||||
.xin1x:
|
||||
movl %esi, %eax
|
||||
movl %esi, %eax
|
||||
|
||||
movl $0x4000, %edx
|
||||
movb %ah, %al
|
||||
.testx1:
|
||||
outb %al, $0x80
|
||||
decl %edx
|
||||
jnz .testx1
|
||||
|
||||
movl (%esi), %eax
|
||||
cmpb 0xff, %al
|
||||
je .xin2 /* dont show */
|
||||
movl $0x4000, %edx
|
||||
movb %ah, %al
|
||||
.testx1:
|
||||
outb %al, $0x80
|
||||
decl %edx
|
||||
jnz .testx1
|
||||
|
||||
movl (%esi), %eax
|
||||
cmpb 0xff, %al
|
||||
je .xin2 /* dont show */
|
||||
|
||||
movl $0x4000, %edx
|
||||
movl $0x4000, %edx
|
||||
.testx2:
|
||||
outb %al, $0x80
|
||||
decl %edx
|
||||
jnz .testx2
|
||||
|
||||
outb %al, $0x80
|
||||
decl %edx
|
||||
jnz .testx2
|
||||
|
||||
.xin2: decl %ecx
|
||||
je .xout1x
|
||||
add $4, %esi
|
||||
jmp .xin1x
|
||||
je .xout1x
|
||||
add $4, %esi
|
||||
jmp .xin1x
|
||||
.xout1x:
|
||||
|
||||
#endif
|
||||
|
|
@ -443,24 +442,24 @@ lout:
|
|||
/* Store zero for the unused init_detected parameter. */
|
||||
pushl %eax
|
||||
|
||||
/* Restore the BIST result */
|
||||
/* Restore the BIST result. */
|
||||
movl %ebp, %eax
|
||||
/* We need to set ebp ? No need */
|
||||
movl %esp, %ebp
|
||||
pushl %eax /* bist */
|
||||
call stage1_main
|
||||
/* We will not go back */
|
||||
fixed_mtrr_msr:
|
||||
.long 0x250, 0x258, 0x259
|
||||
.long 0x268, 0x269, 0x26A
|
||||
.long 0x26B, 0x26C, 0x26D
|
||||
.long 0x26E, 0x26F
|
||||
var_mtrr_msr:
|
||||
.long 0x200, 0x201, 0x202, 0x203
|
||||
.long 0x204, 0x205, 0x206, 0x207
|
||||
.long 0x208, 0x209, 0x20A, 0x20B
|
||||
.long 0x20C, 0x20D, 0x20E, 0x20F
|
||||
.long 0x000 /* NULL, end of table */
|
||||
fixed_mtrr_msr:
|
||||
.long 0x250, 0x258, 0x259
|
||||
.long 0x268, 0x269, 0x26A
|
||||
.long 0x26B, 0x26C, 0x26D
|
||||
.long 0x26E, 0x26F
|
||||
var_mtrr_msr:
|
||||
.long 0x200, 0x201, 0x202, 0x203
|
||||
.long 0x204, 0x205, 0x206, 0x207
|
||||
.long 0x208, 0x209, 0x20A, 0x20B
|
||||
.long 0x20C, 0x20D, 0x20E, 0x20F
|
||||
.long 0x000 /* NULL, end of table */
|
||||
|
||||
/* Reset vector. */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue