mb/google/nissa: Create pujjogatwin variant
Create the pujjogatwin variant of nissa reference board by copying the pujjoga files to a new directory named for the variant. The difference between pujjoga and pujjogatwin is that pujjogatwin use Twin Lake CPU and firmware config, so copying the pujjoga setting files to create new variant. BUG=b:381152086 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJOGATWIN Change-Id: I345ce463699840b10016555bb104a16968e7a8c1 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85329 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Roger Wang
Eric Lai
parent
c0ccace4d5
commit
cda1e7e553
6 changed files with 502 additions and 0 deletions
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@ -442,6 +442,15 @@ config BOARD_GOOGLE_PUJJOGA
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select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
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select HAVE_WWAN_POWER_SEQUENCE
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config BOARD_GOOGLE_PUJJOGATWIN
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select BOARD_GOOGLE_BASEBOARD_NISSA
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select DRIVERS_GENERIC_GPIO_KEYS
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select CHROMEOS_WIFI_SAR if CHROMEOS
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select DRIVERS_I2C_SX9324
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select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
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select HAVE_WWAN_POWER_SEQUENCE
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select SOC_INTEL_TWINLAKE
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config BOARD_GOOGLE_QUANDISO
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select BOARD_GOOGLE_BASEBOARD_NISSA
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select CHROMEOS_WIFI_SAR if CHROMEOS
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@ -763,6 +772,7 @@ config DRIVER_TPM_I2C_BUS
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default 0x0 if BOARD_GOOGLE_YAVILLA
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default 0x1 if BOARD_GOOGLE_ZYDRON
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default 0x0 if BOARD_GOOGLE_TELITH
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default 0x0 if BOARD_GOOGLE_PUJJOGATWIN
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config DRIVER_TPM_I2C_ADDR
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hex
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@ -839,8 +849,10 @@ config TPM_TIS_ACPI_INTERRUPT
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default 13 if BOARD_GOOGLE_YAVILLA
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default 13 if BOARD_GOOGLE_ZYDRON
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default 13 if BOARD_GOOGLE_TELITH
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default 13 if BOARD_GOOGLE_PUJJOGATWIN
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree_pujjogatwin.cb" if BOARD_GOOGLE_PUJJOGATWIN
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config MAINBOARD_DIR
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@ -923,6 +935,7 @@ config MAINBOARD_PART_NUMBER
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default "Zydron" if BOARD_GOOGLE_ZYDRON
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default "Pujjoga" if BOARD_GOOGLE_PUJJOGA
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default "Telith" if BOARD_GOOGLE_TELITH
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default "Pujjogatwin" if BOARD_GOOGLE_PUJJOGATWIN
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config VARIANT_DIR
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default "agah" if BOARD_GOOGLE_AGAH
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@ -993,6 +1006,7 @@ config VARIANT_DIR
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default "yavista" if BOARD_GOOGLE_YAVISTA
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default "pujjoga" if BOARD_GOOGLE_PUJJOGA
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default "telith" if BOARD_GOOGLE_TELITH
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default "pujjoga" if BOARD_GOOGLE_PUJJOGATWIN
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config VBOOT
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select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO)
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@ -200,6 +200,9 @@ config BOARD_GOOGLE_SUNDANCE
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config BOARD_GOOGLE_PUJJOGA
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bool "-> Pujjoga"
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config BOARD_GOOGLE_PUJJOGATWIN
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bool "-> Pujjogatwin"
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config BOARD_GOOGLE_ORISA
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bool "-> Orisa"
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@ -7,3 +7,4 @@ SPD_SOURCES =
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SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068, K3KL8L80CM-MGCT, MT62F1G32D2DS-026 WT:B
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SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E
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SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 2(0b0010) Parts = K3KL6L60GM-MGCT
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SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 3(0b0011) Parts = H58G56CK8BX146
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@ -9,3 +9,4 @@ H9JCNNNBK3MLYR-N6E 1 (0001)
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K3KL6L60GM-MGCT 2 (0010)
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K3KL8L80CM-MGCT 0 (0000)
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MT62F1G32D2DS-026 WT:B 0 (0000)
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H58G56CK8BX146 3 (0011)
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@ -14,3 +14,4 @@ H9JCNNNBK3MLYR-N6E
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K3KL6L60GM-MGCT
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K3KL8L80CM-MGCT
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MT62F1G32D2DS-026 WT:B
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H58G56CK8BX146
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@ -0,0 +1,482 @@
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fw_config
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field WWAN 3 4
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option WWAN_ABSENT 0
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option LTE_PRESENT 1
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option 5G_PRESENT 2
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end
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field WIFI_SAR_ID 18 21
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option WIFI_SAR_TABLE_AX211 0
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option WIFI_SAR_TABLE_AX203 1
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end
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end
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chip soc/intel/alderlake
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# Acoustic settings
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register "acoustic_noise_mitigation" = "1"
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register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
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register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
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register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
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register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
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register "PreWake" = "100"
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register "sagv" = "SaGv_Enabled"
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# EMMC Tx CMD Delay
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# Refer to EDS-Vol2-42.3.7.
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# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
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# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
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register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-42.3.8.
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# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
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# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-42.3.9.
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# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
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# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
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# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
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# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-42.3.10.
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# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
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# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
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# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
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# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
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register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-42.3.12.
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# [17:16] stands for Rx Clock before Output Buffer,
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# 00: Rx clock after output buffer,
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# 01: Rx clock before output buffer,
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# 10: Automatic selection based on working mode.
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# 11: Reserved
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
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# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023"
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# EMMC Rx Strobe Delay
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# Refer to EDS-Vol2-42.3.11.
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# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
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# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
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register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515"
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# SOC Aux orientation override:
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# This is a bitfield that corresponds to up to 4 TCSS ports.
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# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
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# TcssAuxOri = 0101b
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# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
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# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
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# motherboard to USBC connector
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register "tcss_aux_ori" = "5"
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register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
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register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB-A1
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UF Camera
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN
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# Configure external V1P05/Vnn/VnnSx Rails for Pujjoga
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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}"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C1 | Touchscreen |
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#| I2C2 | Sub-board(PSensor)/WCAM |
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#| I2C3 | Audio |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[0] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST_PLUS,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST_PLUS,
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.scl_lcnt = 55,
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.scl_hcnt = 30,
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.sda_hold = 7,
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}
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 157,
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.scl_hcnt = 79,
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.sda_hold = 7,
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}
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 157,
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.scl_hcnt = 79,
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.sda_hold = 7,
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}
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 158,
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.scl_hcnt = 79,
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.sda_hold = 7,
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}
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 158,
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.scl_hcnt = 79,
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.sda_hold = 7,
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}
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},
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}"
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device domain 0 on
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""CPU""
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register "options.tsr[1].desc" = ""DDR""
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register "options.tsr[2].desc" = ""5VCharger""
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 90, 10000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 60000),
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[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 15000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 3000,
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.max_power = 6000,
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.time_window_min = 1 * MSECS_PER_SEC,
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.time_window_max = 1 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 25000,
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.max_power = 25000,
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.time_window_min = 1 * MSECS_PER_SEC,
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.time_window_max = 1 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 3000 },
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[1] = { 24, 2000 },
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[2] = { 16, 1500 },
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[3] = { 8, 1000 }
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}"
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device generic 0 on end
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end
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end
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device ref i2c1 on
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chip drivers/i2c/hid
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register "generic.hid" = ""GDIX0000""
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register "generic.desc" = ""Goodix Touchscreen""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
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register "generic.detect" = "1"
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register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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register "generic.enable_delay_ms" = "20"
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register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
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register "generic.reset_delay_ms" = "180"
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register "generic.reset_off_delay_ms" = "3"
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register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
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register "generic.stop_off_delay_ms" = "1"
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register "generic.has_power_resource" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 5d on end
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end
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chip drivers/generic/gpio_keys
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register "name" = ""PENH""
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register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"
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register "key.wake_gpe" = "GPE0_DW2_15"
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register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
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register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
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register "key.dev_name" = ""EJCT""
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register "key.linux_code" = "SW_PEN_INSERTED"
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register "key.linux_input_type" = "EV_SW"
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register "key.label" = ""pen_eject""
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device generic 0 on end
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end
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end
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device ref i2c2 on
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chip drivers/i2c/sx9324
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register "desc" = ""SAR Proximity Sensor""
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
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register "speed" = "I2C_SPEED_FAST"
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register "uid" = "1"
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register "reg_gnrl_ctrl0" = "0x16"
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register "reg_gnrl_ctrl1" = "0x21"
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register "reg_afe_ctrl0" = "0x00"
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register "reg_afe_ctrl1" = "0x10"
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register "reg_afe_ctrl2" = "0x00"
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register "reg_afe_ctrl3" = "0x00"
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register "reg_afe_ctrl4" = "0x47"
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register "reg_afe_ctrl5" = "0x00"
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register "reg_afe_ctrl6" = "0x00"
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register "reg_afe_ctrl7" = "0x47"
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register "reg_afe_ctrl8" = "0x12"
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register "reg_afe_ctrl9" = "0x08"
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register "reg_afe_ph0" = "0x3d"
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register "reg_afe_ph1" = "0x1b"
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register "reg_afe_ph2" = "0x1f"
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register "reg_afe_ph3" = "0x3d"
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register "reg_prox_ctrl0" = "0x0b"
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register "reg_prox_ctrl1" = "0x0a"
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register "reg_prox_ctrl2" = "0x90"
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register "reg_prox_ctrl3" = "0x60"
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register "reg_prox_ctrl4" = "0x0c"
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register "reg_prox_ctrl5" = "0x00"
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register "reg_prox_ctrl6" = "0x19"
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register "reg_prox_ctrl7" = "0x58"
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register "reg_adv_ctrl0" = "0x00"
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register "reg_adv_ctrl1" = "0x00"
|
||||
register "reg_adv_ctrl2" = "0x00"
|
||||
register "reg_adv_ctrl3" = "0x00"
|
||||
register "reg_adv_ctrl4" = "0x00"
|
||||
register "reg_adv_ctrl5" = "0x05"
|
||||
register "reg_adv_ctrl6" = "0x00"
|
||||
register "reg_adv_ctrl7" = "0x00"
|
||||
register "reg_adv_ctrl8" = "0x00"
|
||||
register "reg_adv_ctrl9" = "0x00"
|
||||
register "reg_adv_ctrl10" = "0x00"
|
||||
register "reg_adv_ctrl11" = "0x00"
|
||||
register "reg_adv_ctrl12" = "0x00"
|
||||
register "reg_adv_ctrl13" = "0x00"
|
||||
register "reg_adv_ctrl14" = "0x80"
|
||||
register "reg_adv_ctrl15" = "0x0c"
|
||||
register "reg_adv_ctrl16" = "0x08"
|
||||
register "reg_adv_ctrl17" = "0x56"
|
||||
register "reg_adv_ctrl18" = "0x33"
|
||||
register "reg_adv_ctrl19" = "0x00"
|
||||
register "reg_adv_ctrl20" = "0x00"
|
||||
|
||||
register "ph0_pin" = "{1, 3, 3}"
|
||||
register "ph1_pin" = "{3, 2, 1}"
|
||||
register "ph2_pin" = "{3, 3, 1}"
|
||||
register "ph3_pin" = "{1, 3, 3}"
|
||||
register "ph01_resolution" = "1024"
|
||||
register "ph23_resolution" = "1024"
|
||||
register "startup_sensor" = "1"
|
||||
register "ph01_proxraw_strength" = "3"
|
||||
register "ph23_proxraw_strength" = "2"
|
||||
register "avg_pos_strength" = "256"
|
||||
register "cs_idle_sleep" = ""hi-z""
|
||||
register "int_comp_resistor" = ""lowest""
|
||||
register "input_precharge_resistor_ohms" = "4000"
|
||||
register "input_analog_gain" = "1"
|
||||
device i2c 28 on
|
||||
probe WWAN LTE_PRESENT
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref i2c3 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""RTL5682""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Headset Codec""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
|
||||
# Set the jd_src to RT5668_JD1 for jack detection
|
||||
register "property_count" = "1"
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
device i2c 1a on end
|
||||
end
|
||||
chip drivers/generic/alc1015
|
||||
register "hid" = ""RTL1019""
|
||||
register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c5 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "wake" = "GPE0_DW2_14"
|
||||
register "detect" = "1"
|
||||
device i2c 15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""SYNA0000""
|
||||
register "generic.cid" = ""ACPI0C50""
|
||||
register "generic.desc" = ""Synaptics Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "generic.wake" = "GPE0_DW2_14"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 0x2c on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp4 on
|
||||
# PCIe 4 WLAN
|
||||
register "pch_pcie_rp[PCH_RP(4)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_DW1_03"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp7 off end
|
||||
device ref pch_espi on
|
||||
chip ec/google/chromeec
|
||||
use conn0 as mux_conn[0]
|
||||
use conn1 as mux_conn[1]
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port1 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port2 as usb2_port
|
||||
use tcss_usb3_port2 as usb3_port
|
||||
device generic 1 alias conn1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C1 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref tcss_usb3_port2 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C1 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref usb2_port2 on end
|
||||
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A1 (DB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb2_port4 on end
|
||||
end
|
||||
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port5 on
|
||||
probe WWAN LTE_PRESENT
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 UFC""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 WFC""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port8 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""CNVi Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A1 (DB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb3_port3 on
|
||||
probe WWAN LTE_PRESENT
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
Loading…
Add table
Add a link
Reference in a new issue