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mb/asrock: Add Asrock Industrial IMB-1222 motherboard

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ASRock IMB-1222 Intel Comet Lake-S Q470E industrial thin mini-ITX
motherboard [1].

Working:
- Dual Channel DDR4 2933/2666/2400 MHz;
- Intel UHD Graphics (VGA Option ROM, libgfxinit, GOP driver);
- DP (both), HDMI;
- PCIe x16 Slot (Gen3);
- SATA ports;
- USB 2.0 ports;
- USB 3.2 ports;
- M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0 and CNVi);
- M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1);
- M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3);
- LAN1 Intel I225LM/I225V, 10/100/1000/2500 Mbps;
- LAN2 Intel I219LM, 10/100/1000 Mbps;
- Realtek ALC887 HD Audio (line-out, mic-in);
- COM 1/2/3/4 ports;
- onboard speaker;
- HWM/FANs control (fintek f81966);
- S3 suspend and wake;
- TPM;
- disabling ME with me_cleaner [2];

Payload:
- Linux as payload;
- LinuxBoot;
- SeaBIOS;
- edk2 [3].

Bootable OS:
- Ubuntu 22.04 (Linux 6.5.0-15-generic);
- Ubuntu 24.04 (Linux 6.8.0-41-generic);
- Microsoft Windows 10 Pro (10.0.19045.4780, 22H2 2022);
- Andoid 13, Bliss OS x86_64 (16.9.7, Linux 6.1.112-gloria-xanmod1).

Unknown/untested:
- USB3.0 in M.2 Key-B 3042/3052 slot;
- eDP/LVDS;
- PCIe riser cards;
- SPDIF.

There is no schematic/boardview, reverse engineering only.
This port is based on system76/bonw14 because it has a similar topology.

[1] https://web.archive.org/web/20220924171403/https://
www.asrockind.com/en-gb/IMB-1222

[2] XutaxKamay's me_cleaner fork,
https://github.com/XutaxKamay/me_cleaner, v1.2-9-gf20532d

[3] MrChromebox's edk2 fork, https://github.com/mrchromebox/edk2
uefipayload_2408 branch

Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83107
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maxim Polyakov 2024-06-17 22:22:14 +03:00 • committed by Felix Singer
commit c1caa33a2d
25 changed files with 1372 additions and 0 deletions
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198
Documentation/mainboard/asrock/imb-1222.md Normal file
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# ASRock Industrial IMB-1222 Thin Mini-ITX Motherboard
This page describes how to run coreboot on the [ASRock IMB-1222].
## Technology
```{eval-rst}
+------------+---------------------------------------------------------------+
| CPU | Intel 10th Gen (Comet lake-S) Core Processors (LGA-1200) |
| | CPUs over 80W will be limited due to power design |
+------------+---------------------------------------------------------------+
| DRAM | 2 SO-DIMM slots, DDR4 2933/2666/2400 MHz |
+------------+---------------------------------------------------------------+
| Chipset | Intel Q470E |
+------------+---------------------------------------------------------------+
| Super I/O | Fintek F81966 |
+------------+---------------------------------------------------------------+
| TPM | Infineon SLB 9670VQ2.0 |
+------------+---------------------------------------------------------------+
| Boot | USB, SATA, NVMe |
+------------+---------------------------------------------------------------+
| Power | Laptop Power Supply: |
| | - 12V DC-in (IMB-1222) |
| | - 12V~28V DC-in (IMB-1222-WV) |
+------------+---------------------------------------------------------------+
```
```text
+--------------+ +---------------------------+ +---------------+
| eDP |------------------------| |----| DDR4 SODIMM |
+--------------+ | | +---------------+
+--------------+ +--------------+ | | +---------------+
| HDMI |----| ITE IT6563 |----| |----| DDR4 SODIMM |
+--------------+ +--------------+ | | +---------------+
+--------------+ | Intel 10th Gen |
| Display Port |------------------------| (Comet lake-S) |
+--------------+ | Core Processors |
+--------------+ | LGA-1200 |
| Display Port |------------------------| |
+--------------+ | |
+--------------+ +--------------+ | | +---------------+
| LVDS |----| CH7511B-BF |----| |----| PCIe Gen3 x16 |
+--------------+ +--------------+ +---------------------------+ +---------------+
|
|
+------------------+ +---------------------------+ +---------------+
| 4 x USB 3.2 Gen1 | | | | 2 x SATA |
| Connector |--------------------| |----| Connector |
+------------------+ | | +---------------+
+------------------+ | | +---------------+
| 2 x USB 3.2 Gen1 | | | | M.2 KeyM SATA |
| Header |--------------------| Intel Q470E PCH |----| PCIe Gen3x4 |
+------------------+ | | +---------------+
+--------------+ | | +---------------+
| 2 x USB 2.0 | | | | M.2 Key E |
| Header |------------------------| |----| PCIe Gen3 x1/ |
+--------------+ | | | CNVi/USB2.0 |
+--------------+ +--------------+ | | +---------------+
| RJ45 |----| I225LM/I225V |----| | +---------------+
+--------------+ +--------------+ | | | M.2 Key B |
+--------------+ +--------------+ | |----| PCIe Gen3 x1/ |
| RJ45 |----| I219LM |----| | | USB3.0/USB2.0 |
+--------------+ +--------------+ | | +---------------+
+--------------+ +--------------+ | | +---------------+
| Mic-in | | Realtek | | | | TPM INFINEON |
| Line-out |----| ALC887 |----| |----| SLB 9670VQ2.0 |
| SPDIF | +--------------+ | | +---------------+
+--------------+ | +---------------------------+
+--------------+ |
| ALC122 | | LPC
+--------------+ +--------------+
+-----------------------+ +--------------+ | | +------------+
| 2 x COM RS232/422/482 |---| ST3243E |---| Fintek |----| CPU FAN x1 |
+-----------------------+ +--------------+ | F81966 | +------------+
+-----------------------+ +--------------+ | SuperIO | +------------+
| 2 x COM RS232 |---| ST3243E |---| |----| NCT 3941SA |
+-----------------------+ +--------------+ +--------------+ +------------+
| |
+--------------+ +------------+
| 8 x GPIO | | CHA FAN x1 |
+--------------+ +------------+
```
This port was created without a schematic/boardview, reverse engineering only.
Feel free to make changes.
## Building coreboot
The following commands will help quickly configure and build a project for this board:
```bash
make distclean
touch .config
./util/scripts/config --enable VENDOR_ASROCK
./util/scripts/config --enable BOARD_ASROCK_IMB_1222
make olddefconfig
make
```
## Payloads
```{eval-rst}
+---------------+------+---------+-----------+
| OS / Payload | EDK2 | SeaBIOS | LinuxBoot |
+===============+======+=========+===========+
| Ubuntu 22.04 | V | V | V |
+---------------+------+---------+-----------+
| Ubuntu 24.04 | V | V | V |
+---------------+------+---------+-----------+
| Windows 10 | V | | |
+---------------+------+---------+-----------+
| Android 13 | | V | |
+---------------+------+---------+-----------+
```
- LinuxBoot/Linux as payload;
- SeaBIOS (1.16.3);
- edk2 [MrChromebox fork] (uefipayload_2408).
- Ubuntu 22.04 (Linux 6.5.0-15-generic);
- Ubuntu 24.04 (Linux 6.8.0-41-generic);
- Microsoft Windows 10 Pro (10.0.19045.4780, 22H2 2022);
- Andoid 13, [Bliss OS] x86_64 (16.9.7, Linux 6.1.112-gloria-xanmod1).
## Flashing coreboot
```{eval-rst}
+---------------------+--------------------------+
| Type | Value |
+=====================+==========================+
| Socketed flash | yes |
+---------------------+--------------------------+
| Model | W25Q256JV |
| | MX25L25673G |
+---------------------+--------------------------+
| Size | 32 MiB |
+---------------------+--------------------------+
| Package | WSON-8 8x6 mm |
+---------------------+--------------------------+
| Write protection | chipset PRR |
+---------------------+--------------------------+
| Dual BIOS feature | no |
+---------------------+--------------------------+
| Internal flashing | after flashing coreboot |
+---------------------+--------------------------+
```
The SPI flash can be accessed using [flashrom]. By default, only the
BIOS region of the flash is writable:
```bash
flashrom -p internal -N -w coreboot.rom --ifd -i bios
```
If you wish to change any other region, such as the Management Engine
or firmware descriptor, then an external programmer is required. More
information about this [here](../../tutorial/flashing_firmware/index.md).
## Working
- Dual Channel DDR4 2933/2666/2400 MHz;
- Intel UHD Graphics:
- DP (both);
- HDMI;
- VGA Option ROM;
- libgfxinit;
- GOP;
- PCIe x16 Slot (Gen3);
- SATA ports;
- USB 2.0 ports;
- USB 3.2 ports;
- M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0 and CNVi);
- M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1);
- M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3);
- LAN1 Intel I225LM/I225V, 10/100/1000/2500 Mbps;
- LAN2 Intel I219LM, 10/100/1000 Mbps;
- Realtek ALC887 HD Audio (line-out, mic-in);
- COM 1/2/3/4 ports (Fintek f81966);
- onboard speaker;
- HWM/FANs control (Fintek f81966);
- S3 suspend and wake;
- TPM;
- disabling ME with me_cleaner [XutaxKamay fork] (v1.2-9-gf20532d).
## Unknown/untested
- USB 3.0 in M.2 Key-B 3042/3052 slot (currently disabled);
- eDP/LVDS (currently disabled);
- PCIe riser cards;
- SPDIF;
- SATA RAID.
[ASRock IMB-1222]: https://web.archive.org/web/20220924171403/https://www.asrockind.com/en-gb/IMB-1222
[flashrom]: https://flashrom.org/Flashrom
[MrChromebox fork]: https://github.com/MrChromebox/edk2
[XutaxKamay fork]: https://github.com/XutaxKamay/me_cleaner
[Bliss OS]: https://blissos.org/

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Documentation/mainboard/index.md
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@ -33,6 +33,7 @@ pademelon <amd/pademelon/pademelon.md>
H77 Pro4-M <asrock/h77pro4-m.md>
H81M-HDS <asrock/h81m-hds.md>
H110M-DVS <asrock/h110m-dvs.md>
IMB-1222 <asrock/imb-1222.md>
```
## ASUS

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## SPDX-License-Identifier: GPL-2.0-or-later
if BOARD_ASROCK_IMB_1222
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_32768
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select MAINBOARD_HAS_LIBGFXINIT
select MAINBOARD_USES_IFD_GBE_REGION
select MEMORY_MAPPED_TPM
select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select SOC_INTEL_CANNONLAKE_PCH_H
select SOC_INTEL_COMETLAKE_S
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SPD_READ_BY_WORD
select SUPERIO_FINTEK_COMMON_PRE_RAM
config MAINBOARD_DIR
default "asrock/imb-1222"
config MAINBOARD_PART_NUMBER
default "imb-1222"
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Asrock"
config MAINBOARD_VERSION
default "imb-1222"
config CBFS_SIZE
default 0xc00000
config CONSOLE_POST
default y
config DIMM_MAX
default 2
config POST_DEVICE
default n
config BEEP_ON_BOOT
bool "Beep on successful boot"
default y
help
Make the platform beep using the PC speaker in final coreboot phase.
May serve as a useful indicator in headless mode that platform is
properly booting.
config BEEP_ON_PANIC
bool "Beep on panic"
default y
help
Beep when encountered a fatal error.
endif

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src/mainboard/asrock/imb-1222/Kconfig.name Normal file
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## SPDX-License-Identifier: GPL-2.0-or-later
config BOARD_ASROCK_IMB_1222
bool "IMB-1222"

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src/mainboard/asrock/imb-1222/Makefile.mk Normal file
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## SPDX-License-Identifier: GPL-2.0-only
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
bootblock-y += bootblock.c
bootblock-y += superio.c
romstage-y += romstage.c
ramstage-y += ramstage.c
ramstage-y += gpio.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
all-y += beep.c
all-y += panic.c
smm-y += beep.c
smm-y += panic.c

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/* SPDX-License-Identifier: GPL-2.0-only */
Scope (\_SB) {
#include "sleep.asl"
}

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Method called from _PTS prior to enter sleep state */
Method (MPTS, 1) {}
/* Method called from _WAK prior to wakeup */
Method (MWAK, 1) {
Return(Package(){0, 0})
}

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src/mainboard/asrock/imb-1222/beep.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <delay.h>
#include <pc80/i8254.h>
#include <gpio.h>
#include <mainboard/beep.h>
#define LED_GPIO_PAD GPP_E8
#define SPKR_GPIO_PAD GPP_B14
static const struct pad_config spkr_led_cfg_tbl[] = {
PAD_CFG_GPO(LED_GPIO_PAD, 0, PLTRST), /* GPIO */
PAD_CFG_NF(SPKR_GPIO_PAD, DN_20K, PLTRST, NF1), /* SPKR */
};
static const struct pad_config sata_led_cfg_tbl[] = {
PAD_CFG_NF(LED_GPIO_PAD, UP_5K, PLTRST, NF1), /* SATALED# */
};
static void config_gpio_spkr_led(void)
{
gpio_configure_pads(spkr_led_cfg_tbl, ARRAY_SIZE(spkr_led_cfg_tbl));
}
static void config_gpio_sata_led(void)
{
gpio_configure_pads(sata_led_cfg_tbl, ARRAY_SIZE(sata_led_cfg_tbl));
}
static void blink_sata_led(unsigned int on)
{
gpio_set(LED_GPIO_PAD, on ^ 1);
}
void mainboard_beep_and_blink_on_panic_once(void)
{
const unsigned int duration_msec = 300;
static bool once = false;
if (!once) {
config_gpio_spkr_led();
once = true;
}
blink_sata_led(1);
if (CONFIG(BEEP_ON_PANIC))
beep(800, duration_msec);
else
mdelay(duration_msec);
blink_sata_led(0);
}
void mainboard_beep_and_blink_on_boot_once(void)
{
const unsigned int duration_msec = 500;
if (CONFIG(BEEP_ON_BOOT)) {
config_gpio_spkr_led();
blink_sata_led(1);
beep(600, duration_msec);
blink_sata_led(0);
config_gpio_sata_led();
}
}

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src/mainboard/asrock/imb-1222/board_info.txt Normal file
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Vendor name: Asrock Industrial
Board name: IMB-1222
Category: desktop
Board URL: https://web.archive.org/web/20220924171403/https://www.asrockind.com/en-gb/IMB-1222
Release year: 2020
ROM package: WSON-8
ROM protocol: SPI
ROM socketed: y
Flashrom support: y

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src/mainboard/asrock/imb-1222/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <mainboard/superio.h>
void bootblock_mainboard_early_init(void)
{
mainboard_superio_init();
}

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src/mainboard/asrock/imb-1222/cmos.default Normal file
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boot_option=Fallback
debug_level=Debug
me_state=Disable

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src/mainboard/asrock/imb-1222/cmos.layout Normal file
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# SPDX-License-Identifier: GPL-2.0-only
entries
0 384 r 0 reserved_memory
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# RTC_CLK_ALTCENTURY
400 8 r 0 century
412 4 e 6 debug_level
416 1 e 2 me_state
417 3 h 0 me_state_counter
904 80 h 0 ramtop
984 16 h 0 check_sum
enumerations
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 408 983 984

BIN
src/mainboard/asrock/imb-1222/data.vbt Normal file
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src/mainboard/asrock/imb-1222/devicetree.cb Normal file
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## SPDX-License-Identifier: GPL-2.0-or-later
chip soc/intel/cannonlake
# CPU (soc/intel/cannonlake/cpu.c)
# Power limit
# CPUs over 80W will be limited due to power design
register "power_limits_config" = "{
.tdp_pl1_override = 80,
.tdp_pl2_override = 80,
}"
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "true"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
# Misc
register "AcousticNoiseMitigation" = "1"
# Power
register "PchPmSlpS3MinAssert" = "3" # 50ms
register "PchPmSlpS4MinAssert" = "1" # 1s
register "PchPmSlpSusMinAssert" = "4" # 4s
register "PchPmSlpAMinAssert" = "4" # 2s
# Thermal
register "tcc_offset" = "13"
# PM Util (soc/intel/cannonlake/pmutil.c)
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
#
# With vendor firmware, MISCCFG register = 0x0e06923b
# (offset 10h, p.1234, Doc#620855-002):
# GPE0_DW0: [11:8] 2h -> GPP_C[23:0] mapped to GPE[23:0]
# GPE0_DW1: [15:12] 9h -> GPP_K[23:0] mapped to GPE[55:32]
# GPE0_DW2: [19:16] 6h -> GPP_E[23:0] mapped to GPE[87:64]
register "gpe0_dw0" = "PMC_GPP_C"
register "gpe0_dw1" = "PMC_GPP_K"
register "gpe0_dw2" = "PMC_GPP_E"
# Actual device tree (override src/soc/intel/cannonlake/chipset_pch_h.cb)
device domain 0 on
subsystemid 1849 9b73 inherit
device ref peg0 on # PCIe x16 Gen3
register "PcieClkSrcUsage[0]" = "0x41"
register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "PCIE16X" "SlotDataBusWidth16X"
end
device ref igpu on
# FIXME: EDP should be enabled as soon as it is tested
register "DdiPortEdp" = "0"
register "DdiPortBHpd" = "1"
register "DdiPortBDdc" = "1"
register "DdiPortCHpd" = "1"
register "DdiPortCDdc" = "1"
register "DdiPortDHpd" = "1"
register "DdiPortDDdc" = "1"
end
device ref dptf on end
device ref thermal on end
device ref xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* Rear (USB3_1) */
[1] = USB2_PORT_MID(OC_SKIP), /* Rear (USB3_2) */
[2] = USB2_PORT_MID(OC_SKIP), /* Front (USB3_3) */
[3] = USB2_PORT_MID(OC_SKIP), /* Front (USB3_4) */
[4] = USB2_PORT_MID(OC_SKIP), /* Rear (USB3_5) */
[5] = USB2_PORT_MID(OC_SKIP), /* Rear (USB3_6) */
[7] = USB2_PORT_MID(OC_SKIP), /* Front (USB2_8_9) */
[8] = USB2_PORT_MID(OC_SKIP), /* Front (USB2_8_9) */
[10] = USB2_PORT_MID(OC_SKIP), /* Front (USB2_11_12) */
[11] = USB2_PORT_MID(OC_SKIP), /* Front (USB2_11_12) */
[13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth (M.2 Key-E 2230) */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* Rear (USB3_1) */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* Rear (USB3_2) */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* Front (USB3_3) */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* Front (USB3_4) */
[6] = USB3_PORT_DEFAULT(OC_SKIP), /* Rear (USB3_5) */
[7] = USB3_PORT_DEFAULT(OC_SKIP), /* Rear (USB3_6) */
}"
# ACPI (src/drivers/usb/acpi/usb_acpi.c)
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3_1 Type-A Rear Top""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 0)"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3_1 Type-A Rear Top""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 0)"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3_2 Type-A Rear Bottom""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 1)"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3_2 Type-A Rear Bottom""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 1)"
device ref usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3_3 Type-A Front""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 2)"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3_3 Type-A Front""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 2)"
device ref usb3_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3_4 Type-A Front""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 3)"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3_4 Type-A Front""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 3)"
device ref usb3_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3_5 Type-A Rear Top""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 4)"
device ref usb2_port5 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3_5 Type-A Rear Top""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 4)"
device ref usb3_port7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3_6 Type-A Rear Bottom""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 5)"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3_6 Type-A Rear Bottom""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(0, 5)"
device ref usb3_port8 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2_8 Front""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(0, 6)"
device ref usb2_port8 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2_9 Front""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(0, 7)"
device ref usb2_port9 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2_11 Front""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(0, 8)"
device ref usb2_port11 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2_12 Front""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(0, 9)"
device ref usb2_port12 on end
end
chip drivers/usb/acpi
register "desc" = ""M.2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "group" = "ACPI_PLD_GROUP(0, 10)"
device ref usb2_port14 on end
end
end
end
end
device ref shared_sram on end
device ref cnvi_wifi on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (CNVi)
chip drivers/wifi/generic
register "wake" = "PME_B0_EN_BIT"
device generic 0 on end
end
end
device ref sata on
register "SataPortsEnable" = "{
[1] = 1, /* SATA 3_1 */
[2] = 1, /* SATA 3_2 */
[4] = 1, /* M.2 Key-M 2242/2260/2280 slot for SSD (SATA) */
}"
end
device ref pcie_rp17 on # M.2 Key-M 2242/2260/2280 slot for SSD (PCIEx4)
register "PcieRpEnable[16]" = "1"
register "PcieRpLtrEnable[16]" = "1"
register "PcieRpSlotImplemented[16]" = "1"
register "PcieClkSrcUsage[7]" = "16"
register "PcieClkSrcClkReq[7]" = "7"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2242/2260/2280 (M2_KEYM1)" "SlotDataBusWidth4X"
end
device ref pcie_rp5 on # Intel Corporation Ethernet Controller I225-LM
register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieClkSrcUsage[3]" = "4"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp6 on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (PCIe x1)
register "PcieRpEnable[5]" = "1"
register "PcieRpSlotImplemented[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieClkSrcUsage[5]" = "5"
register "PcieClkSrcClkReq[5]" = "5"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X"
end
device ref pcie_rp7 on # M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1)
register "PcieRpEnable[6]" = "1"
register "PcieRpSlotImplemented[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieClkSrcUsage[6]" = "6"
register "PcieClkSrcClkReq[6]" = "6"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/B 3042/3052 (M2_KEYB1)" "SlotDataBusWidth1X"
end
device ref lpc_espi on
register "gen1_dec" = "0x00fc0201"
register "gen2_dec" = "0x007c0281"
register "gen3_dec" = "0x000c03e1"
register "gen4_dec" = "0x001c02e1"
# Set LPC Serial IRQ mode
register "serirq_mode" = "SERIRQ_CONTINUOUS"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device ref hda on
register "PchHdaAudioLinkHda" = "1"
end
device ref smbus on end
device ref gbe on
register "PcieClkSrcUsage[4]" = "PCIE_CLK_LAN"
register "PcieClkSrcClkReq[4]" = "4"
end
end
end

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725
)
{
#include <acpi/dsdt_top.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Device (\_SB.PCI0) {
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/cannonlake/acpi/southbridge.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB.PCI0.LPCB) {
#include <drivers/pc80/pc/ps2_controller.asl>
}
#include "acpi/mainboard.asl"
}

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-- SPDX-License-Identifier: GPL-2.0-or-later
with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;
private package GMA.Mainboard is
ports : constant Port_List :=
(HDMI1,
DP2,
DP3,
eDP,
others => Disabled);
end GMA.Mainboard;

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <gpio.h>
#include <mainboard/gpio.h>
/*
* Pad configuration was generated automatically using intelp2m utility
* [*] - allow FSP to configure this pad
*/
static const struct pad_config gpio_table[] = {
/* ------- GPIO Community 0 ------- */
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* RCIN# */
PAD_CFG_NF(GPP_A1, NONE, PLTRST, NF1), /* LAD0 */
PAD_CFG_NF(GPP_A2, NONE, PLTRST, NF1), /* LAD1 */
PAD_CFG_NF(GPP_A3, NONE, PLTRST, NF1), /* LAD2 */
PAD_CFG_NF(GPP_A4, NONE, PLTRST, NF1), /* LAD3 */
PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* LFRAME# */
PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), /* SERIRQ */
PAD_CFG_NF(GPP_A7, NONE, PLTRST, NF1), /* PIRQA# */
PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* CLKRUN# */
PAD_CFG_NF(GPP_A9, NONE, PLTRST, NF1), /* CLKOUT_LPC0 */
PAD_CFG_NF(GPP_A10, NONE, PLTRST, NF1), /* CLKOUT_LPC1 */
PAD_CFG_NF(GPP_A11, NONE, PLTRST, NF1), /* PME# */
PAD_NC(GPP_A12, NONE),
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUSWARN#/SUSPWRDNACK */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUS_STAT# */
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SUSACK# */
PAD_CFG_NF(GPP_A16, NONE, PLTRST, NF1), /* CLKOUT_48 */
PAD_NC(GPP_A17, NONE),
PAD_NC(GPP_A18, NONE),
PAD_NC(GPP_A19, NONE),
PAD_NC(GPP_A20, NONE),
PAD_NC(GPP_A21, NONE),
PAD_NC(GPP_A22, NONE),
PAD_NC(GPP_A23, NONE),
/* ------- GPIO Group GPP_B ------- */
PAD_NC(GPP_B0, NONE),
PAD_CFG_GPO(GPP_B1, 1, PLTRST), /* GPIO */
PAD_NC(GPP_B2, NONE),
PAD_NC(GPP_B3, NONE),
PAD_NC(GPP_B4, NONE),
/* [*] GPP_B5 GPIO/SRCCLKREQ0# */
/* [*] GPP_B6 GPIO/SRCCLKREQ1# */
/* [*] GPP_B7 GPIO/SRCCLKREQ2# */
/* [*] GPP_B8 GPIO/SRCCLKREQ3# */
/* [*] GPP_B9 GPIO/SRCCLKREQ4# */
/* [*] GPP_B10 GPIO/SRCCLKREQ5# */
PAD_NC(GPP_B11, NONE),
PAD_NC(GPP_B12, NONE),
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */
PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* SPKR */
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_CFG_GPO(GPP_B18, 0, PLTRST),
PAD_NC(GPP_B19, NONE),
PAD_NC(GPP_B20, NONE),
PAD_NC(GPP_B21, NONE),
PAD_CFG_GPO(GPP_B22, 0, PLTRST),
PAD_CFG_GPO(GPP_B23, 0, PLTRST),
/* ------- GPIO Community 1 ------- */
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */
PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* GPIO */
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */
PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* GPIO */
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */
PAD_NC(GPP_C8, NONE),
PAD_NC(GPP_C9, NONE),
PAD_NC(GPP_C10, NONE),
PAD_NC(GPP_C11, NONE),
PAD_NC(GPP_C12, NONE),
PAD_NC(GPP_C13, NONE),
PAD_NC(GPP_C14, NONE),
PAD_NC(GPP_C15, NONE),
PAD_NC(GPP_C16, NONE),
PAD_NC(GPP_C17, NONE),
PAD_NC(GPP_C18, NONE),
PAD_NC(GPP_C19, NONE),
PAD_NC(GPP_C20, NONE),
PAD_NC(GPP_C21, NONE),
PAD_NC(GPP_C22, NONE),
PAD_NC(GPP_C23, NONE),
/* ------- GPIO Group GPP_D ------- */
PAD_NC(GPP_D0, NONE),
PAD_NC(GPP_D1, NONE),
PAD_NC(GPP_D2, NONE),
PAD_NC(GPP_D3, NONE),
PAD_NC(GPP_D4, NONE),
PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF3), /* CNV_RF_RESET# */
PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF3), /* MODEM_CLKREQ */
PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), /* I2S2_RXD */
PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), /* I2S2_SCLK */
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),
PAD_NC(GPP_D11, NONE),
PAD_NC(GPP_D12, NONE),
PAD_NC(GPP_D13, NONE),
PAD_NC(GPP_D14, NONE),
PAD_CFG_NF(GPP_D15, NONE, PLTRST, NF4), /* CNV_WFEN */
PAD_CFG_NF(GPP_D16, NONE, PLTRST, NF4), /* CNV_WCEN */
PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), /* DMIC_CLK1 */
PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), /* DMIC_DATA1 */
PAD_CFG_NF(GPP_D19, NONE, PLTRST, NF1), /* DMIC_CLK0 */
PAD_CFG_NF(GPP_D20, NONE, PLTRST, NF1), /* DMIC_DATA0 */
PAD_NC(GPP_D21, NONE),
PAD_NC(GPP_D22, NONE),
PAD_NC(GPP_D23, NONE),
/* ------- GPIO Group GPP_G ------- */
PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPO(GPP_G1, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_G2, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_G3, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_G4, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_G5, 1, DEEP), /* GPIO */
PAD_NC(GPP_G6, NONE),
PAD_NC(GPP_G7, NONE),
/* ------- GPIO Community 2 ------- */
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */
PAD_CFG_NF(GPD1, NONE, RSMRST, NF1), /* ACPRESENT */
PAD_CFG_NF(GPD2, NONE, RSMRST, NF1), /* LAN_WAKE# */
PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), /* PRWBTN# */
PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */
PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */
PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */
PAD_CFG_GPO(GPD7, 1, PLTRST), /* GPIO */
PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */
PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */
PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */
PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), /* LANPHYPC */
/* ------- GPIO Community 3 ------- */
/* ------- GPIO Group GPP_K ------- */
PAD_CFG_GPO(GPP_K0, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K1, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K2, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K3, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K4, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K5, 1, PLTRST), /* GPIO */
PAD_NC(GPP_K6, NONE),
PAD_NC(GPP_K7, NONE),
PAD_CFG_GPO(GPP_K8, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K9, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K10, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K11, 0, PLTRST), /* GPIO */
PAD_CFG_GPI_SCI(GPP_K12, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */
PAD_NC(GPP_K13, NONE), /* GPIO */
PAD_CFG_GPO(GPP_K14, 0, DEEP), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_K15, NONE, PLTRST, OFF, ACPI), /* GPIO */
PAD_CFG_GPO(GPP_K16, 0, PLTRST), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_K17, NONE, PLTRST, OFF, ACPI), /* GPIO */
PAD_NC(GPP_K18, NONE),
PAD_NC(GPP_K19, NONE),
PAD_CFG_GPI_TRIG_OWN(GPP_K20, NONE, PLTRST, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_K21, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_K22, NONE, PLTRST, OFF, ACPI), /* GPIO */
PAD_CFG_GPI_TRIG_OWN(GPP_K23, NONE, PLTRST, OFF, ACPI), /* GPIO */
/* ------- GPIO Group GPP_H ------- */
/* [*] GPP_H0 GPIO/SRCCLKREQ6# */
/* [*] GPP_H1 GPIO/SRCCLKREQ7# */
PAD_NC(GPP_H2, NONE),
PAD_NC(GPP_H3, NONE),
PAD_NC(GPP_H4, NONE),
PAD_NC(GPP_H5, NONE),
PAD_NC(GPP_H6, NONE),
PAD_NC(GPP_H7, NONE),
PAD_NC(GPP_H8, NONE),
PAD_NC(GPP_H9, NONE),
PAD_NC(GPP_H10, NONE),
PAD_NC(GPP_H11, NONE),
PAD_CFG_GPO(GPP_H12, 0, PLTRST), /* GPIO */
PAD_NC(GPP_H13, NONE),
PAD_NC(GPP_H14, NONE),
PAD_NC(GPP_H15, NONE),
PAD_NC(GPP_H16, NONE),
PAD_NC(GPP_H17, NONE),
PAD_NC(GPP_H18, NONE),
PAD_NC(GPP_H19, NONE),
PAD_NC(GPP_H20, NONE),
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
PAD_NC(GPP_H23, NONE),
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1), /* SATAXPCIE0 */
PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1), /* SATAXPCIE1 */
PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1), /* SATAXPCIE2 */
PAD_CFG_GPO(GPP_E3, 1, PLTRST), /* GPIO */
PAD_NC(GPP_E4, NONE),
PAD_CFG_GPI_SMI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */
PAD_CFG_GPI_SMI(GPP_E6, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */
PAD_NC(GPP_E7, NONE),
PAD_CFG_NF(GPP_E8, UP_5K, PLTRST, NF1), /* SATALED# */
PAD_NC(GPP_E9, NONE),
PAD_NC(GPP_E10, NONE),
PAD_NC(GPP_E11, NONE),
PAD_NC(GPP_E12, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_GPO(GPP_F0, 0, PLTRST), /* GPIO */
PAD_CFG_NF(GPP_F1, UP_5K, PLTRST, NF1), /* SATAXPCIE4 */
PAD_CFG_GPO(GPP_F2, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_F3, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_F4, 0, PLTRST), /* GPIO */
PAD_NC(GPP_F5, NONE),
PAD_NC(GPP_F6, NONE),
PAD_NC(GPP_F7, NONE),
PAD_CFG_NF(GPP_F8, NONE, PLTRST, NF1), /* SATA_DEVSLP6 */
PAD_NC(GPP_F9, NONE),
PAD_NC(GPP_F10, NONE),
PAD_NC(GPP_F11, NONE),
PAD_NC(GPP_F12, NONE),
PAD_NC(GPP_F13, NONE),
PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF2), /* PS_ON# */
PAD_NC(GPP_F15, NONE),
PAD_NC(GPP_F16, NONE),
PAD_NC(GPP_F17, NONE),
PAD_NC(GPP_F18, NONE),
PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1), /* eDP_VDDEN */
PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), /* eDP_BKLTEN */
PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), /* eDP_BKLTCTL */
PAD_NC(GPP_F22, NONE),
PAD_CFG_GPO(GPP_F23, 0, PLTRST), /* GPIO */
/* ------- GPIO Community 4 ------- */
/* ------- GPIO Group GPP_I ------- */
PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */
PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPB_HPD1 */
PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), /* DDPB_HPD2 */
PAD_NC(GPP_I3, NONE),
PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), /* EDP_HPD */
PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* DDPB_CTRLCLK */
PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1), /* DDPB_CTRLDATA */
PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* DDPC_CTRLCLK */
PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1), /* DDPC_CTRLDATA */
PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */
PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), /* DDPD_CTRLDATA */
PAD_NC(GPP_I11, NONE),
PAD_CFG_GPO(GPP_I12, 1, PLTRST), /* GPIO */
PAD_NC(GPP_I13, NONE),
PAD_CFG_GPO(GPP_I14, 1, PLTRST), /* GPIO */
/* ------- GPIO Group GPP_J ------- */
PAD_CFG_NF(GPP_J0, NONE, PLTRST, NF1), /* CNV_PA_BLANKING */
PAD_CFG_NF(GPP_J1, NONE, PLTRST, NF2), /* CPU_C10_GATE# */
PAD_NC(GPP_J2, NONE),
PAD_NC(GPP_J3, NONE),
PAD_CFG_NF(GPP_J4, NONE, PLTRST, NF1), /* CNV_BRI_DT */
PAD_CFG_NF(GPP_J5, NONE, PLTRST, NF1), /* CNV_BRI_RSP */
PAD_CFG_NF(GPP_J6, NONE, PLTRST, NF1), /* CNV_RGI_DT */
PAD_CFG_NF(GPP_J7, NONE, PLTRST, NF1), /* CNV_RGI_RSP */
PAD_CFG_NF(GPP_J8, NONE, PLTRST, NF1), /* CNV_MFUART2_RXD */
PAD_CFG_NF(GPP_J9, NONE, PLTRST, NF1), /* CNV_MFUART2_TXD */
PAD_NC(GPP_J10, NONE),
PAD_NC(GPP_J11, NONE),
};
void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x10ec0887, /* Realtek ALC887-VD */
0x1849588a, /* Subsystem ID */
15, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(0, 0x1849588a),
AZALIA_PIN_CFG(0, 0x11, 0x40000000),
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x14, 0x01014020),
AZALIA_PIN_CFG(0, 0x15, 0x90170110),
AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x18, 0x01a19050),
AZALIA_PIN_CFG(0, 0x19, 0x02a19060),
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1b, 0x02214030),
AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1d, 0x4024c601),
AZALIA_PIN_CFG(0, 0x1e, 0x01451140),
AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
0x8086280b, /* Intel Kabylake HDMI */
0x80860101, /* Subsystem ID */
4, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(2, 0x80860101),
AZALIA_PIN_CFG(2, 0x05, 0x18560010),
AZALIA_PIN_CFG(2, 0x06, 0x18560020),
AZALIA_PIN_CFG(2, 0x07, 0x18560030),
};
const u32 pc_beep_verbs[] = {
};
AZALIA_ARRAY_SIZES;

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef IMB_1222_MAINBOARD_BEEP_H
#define IMB_1222_MAINBOARD_BEEP_H
void mainboard_beep_and_blink_on_panic_once(void);
void mainboard_beep_and_blink_on_boot_once(void);
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef IMB_1222_MAINBOARD_GPIO_H
#define IMB_1222_MAINBOARD_GPIO_H
void mainboard_configure_gpios(void);
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef IMB_1222_MAINBOARD_SUPERIO_H
#define IMB_1222_MAINBOARD_SUPERIO_H
void mainboard_superio_init(void);
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <delay.h>
#include <console/console.h>
#include <mainboard/beep.h>
static void panic(void)
{
while (1) {
mainboard_beep_and_blink_on_panic_once();
mdelay(200);
mainboard_beep_and_blink_on_panic_once();
mdelay(200);
mainboard_beep_and_blink_on_panic_once();
delay(1);
}
}
void die_notify(void)
{
if (ENV_POSTCAR)
return;
panic();
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
#include <mainboard/gpio.h>
#include <mainboard/beep.h>
void mainboard_fill_fadt(acpi_fadt_t *fadt)
{
fadt->preferred_pm_profile = PM_DESKTOP;
fadt->iapc_boot_arch |= ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
}
static void mainboard_enable(struct device *dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
static void mainboard_init(void *chip_info)
{
mainboard_configure_gpios();
}
static void mainboard_final(void *unused)
{
mainboard_beep_and_blink_on_boot_once();
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
.final = mainboard_final,
};

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
static const struct cnl_mb_cfg memcfg = {
.spd[0] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa0},
},
.spd[2] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa4},
},
.rcomp_resistor = { 121, 75, 100 },
.rcomp_targets = { 50, 26, 20, 20, 26 },
.dq_pins_interleaved = 1,
.vref_ca_config = 2,
};
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
/* Allow memory clocks higher than 2933 MHz */
memupd->FspmConfig.SaOcSupport = 1;
/* Set primary display to PCIe graphics */
memupd->FspmConfig.PrimaryDisplay = 1;
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pnp.h>
#include <mainboard/superio.h>
#include <superio/hwm5_conf.h>
#include <superio/fintek/common/fintek.h>
/* TODO: move this code to superio/fintek driver */
#define SIO_PORT 0x2e
#define SIO_HWM_BASE 0x290
#define SIO_DEV(n) PNP_DEV(SIO_PORT, SIO_LDN_##n)
/* Fintek F81966 Logical Device Numbers (LDN) */
#define SIO_LDN_GLOBAL 0x00
#define SIO_LDN_LPT 0x03
#define SIO_LDN_HWMON 0x04
#define SIO_LDN_KBC 0x05
#define SIO_LDN_GPIO 0x06
#define SIO_LDN_WDT 0x07
#define SIO_LDN_PME_ACPI_ERP 0x0a
#define SIO_LDN_SPI 0x0f
#define SIO_LDN_UART1 0x10
#define SIO_LDN_UART2 0x11
#define SIO_LDN_UART3 0x12
#define SIO_LDN_UART4 0x13
#define SIO_LDN_UART5 0x14
#define SIO_LDN_UART6 0x15
#define SIO_REG(i, v) {.idx = i, .val = v}
#define SIO_ESEL(i, v, m) {.extra_selector = true, .idx = i, .val = v, .mask = m}
#define SIO_LDN(n) {.idx = 0x07, .val = SIO_LDN_##n}
#define SIO_LDN_EN(v) {.idx = 0x30, .val = v}
/* f81966 Port Select (27h): BANK_PROG_SEL[3-2] CLK_TUNE_PROG_EN[0] */
#define SIO_ESEL_27H(bank, en) { \
.extra_selector = true, \
.idx = 0x27, \
.mask = 0xf2, \
.val = esel_27h_##bank | esel_27h_clk_tune_##en, \
}
/* f81966 Fan Fault Time Register (9Fh): FAN_PROG_SEL[7] */
#define SIO_ESEL_9FH(bank) { \
.extra_selector = true, \
.idx = 0x9f, \
.mask = 0x7f, \
.val = esel_9fh_fan_prog_##bank, \
}
/* PWM duty-cycle */
#define PWM_DC(x) (((x << 8) - x) / 100)
enum esel_27h_bank_prog_sel {
esel_27h_bank0 = 0 << 2,
esel_27h_bank1 = 1 << 2,
esel_27h_bank2 = 2 << 2,
esel_27h_bank3 = 3 << 2,
};
enum esel_27h_clk_tune {
esel_27h_clk_tune_dis = 0,
esel_27h_clk_tune_en = 1,
};
enum esel_9fh_fan_prog {
esel_9fh_fan_prog_bank0 = 0 << 7,
esel_9fh_fan_prog_bank1 = 1 << 7,
};
struct sio_reg {
bool extra_selector;
uint8_t idx;
uint8_t val;
uint8_t mask;
};
static const struct sio_reg ldn_reg_tbl[] = {
SIO_LDN(GLOBAL),
SIO_REG(0x27, 0x80), /* disable 0x80 port */
SIO_REG(0x2d, 0x2e), /* enable KB/Mouse wakeup, 2.8/2.5V hysteresis */
SIO_ESEL_27H(bank0, dis),
SIO_REG(0x29, 0xf0), /* set UART fn pins, TTL level */
SIO_REG(0x2a, 0x45), /* GPIO[10]->LED_VSB, GPIO[11]->LED_VCC */
SIO_REG(0x2c, 0xe3), /* en GPIO 00,01 */
SIO_ESEL_27H(bank2, dis),
SIO_REG(0x2b, 0x03), /* select pin 54 as SCL */
SIO_REG(0x2c, 0x01), /* GPIO[20]->ALERT# */
SIO_ESEL_27H(bank3, dis),
SIO_REG(0x28, 0x59), /* PLL_CNT = (256*48) / 89 = 138 */
SIO_ESEL_27H(bank0, en),
/*
* - GPIO[90]->LDRQ#, GPIO[91]->KBRST#, GPIO[92]->GA20, GPIO[93]->MDATA,
* - GPIO[94]->MCLK, GPIO[95]->FANIN1, GPIO[96]->FANIN2, GPIO[97]->SLCT
*/
SIO_REG(0x2c, 0x00),
SIO_ESEL_27H(bank0, dis),
SIO_LDN(GPIO),
SIO_REG(0x60, 0x02),
SIO_REG(0x61, 0x80), /* base address */
SIO_REG(0xe0, 0x10), /* GPIO[14]->output mode */
SIO_REG(0xe3, 0x10), /* GPIO[14]->is push pull in output mode */
SIO_REG(0xe6, 0x10), /* GPIO[14]->SMI event will set if input is changed */
SIO_REG(0x80, 0xe0), /* GPIO[75,76,77]->is in output mode */
SIO_REG(0x81, 0xe0), /* GPIO[75,76,77]=1 */
SIO_REG(0x88, 0x01), /* GPIO[80]->is in output mode */
SIO_REG(0x89, 0x01), /* GPIO[80]=1 */
SIO_REG(0x8e, 0xff), /* GPIO[80,81,82,83,84,85,86,87]->use SMI event */
SIO_LDN_EN(0x01), /* enable GPIO I/O ports */
SIO_LDN(HWMON),
SIO_REG(0x60, SIO_HWM_BASE >> 8),
SIO_REG(0x61, SIO_HWM_BASE & 0xff),
SIO_LDN_EN(0x01), /* enable hardware monitor */
SIO_LDN(UART1),
SIO_REG(0xf6, 0x23), /* 128-byte FIFO, FIFO threshold will be 4X of RXFTHR */
SIO_LDN_EN(0x01),
SIO_LDN(UART2),
SIO_REG(0xf6, 0x23),
SIO_LDN_EN(0x01),
SIO_LDN(UART3),
SIO_REG(0xf6, 0x23),
SIO_LDN_EN(0x01),
SIO_LDN(UART4),
SIO_REG(0xf6, 0x23),
SIO_LDN_EN(0x01),
};
static const struct sio_reg hwm_reg_tbl[] = {
SIO_REG(0x07, 0x4a), /* MXM address */
SIO_REG(0x0a, 0x01), /* enable PECI access */
SIO_REG(0x0c, 0x64), /* TCC Temperature : CPU_TEMP = TCC_TEMP + PECI Reading */
SIO_REG(0x0f, 0x20), /* digital rate selector (Reserved for Fintek use only) */
SIO_REG(0x6b, 0x00), /* TEMP[1,2] is connected to a thermistor */
SIO_ESEL_9FH(bank0),
/*
* - FAN[1]->open drain, output PWM mode to control Intel 4-wire fans;
* - FAN[2]->push pull, output PWM mode to control fans;
* - FAN[3]->use linear fan application circuit to control speed by power terminal
*/
SIO_REG(0x94, 0x12),
SIO_REG(0x9b, 0x1f), /* FAN[1,2]->duty update rate 20Hz */
SIO_ESEL_9FH(bank1),
SIO_REG(0x9b, 0x55), /* direct load enable for manual duty mode */
SIO_ESEL_9FH(bank0),
SIO_REG(0xa3, 0x75), /* FAN[1] expect PWM duty */
SIO_REG(0xa6, 70), /* VT[1] boundary 1 temperature */
SIO_REG(0xa7, 65), /* VT[1] boundary 2 temperature */
SIO_REG(0xa8, 55), /* VT[1] boundary 3 temperature */
SIO_REG(0xa9, 45), /* VT[1] boundary 4 temperature */
SIO_REG(0xaa, PWM_DC(100)), /* FAN[1] segment 1 speed count */
SIO_REG(0xab, PWM_DC(85)), /* FAN[1] segment 2 speed count */
SIO_REG(0xac, PWM_DC(70)), /* FAN[1] segment 3 speed count */
SIO_REG(0xad, PWM_DC(60)), /* FAN[1] segment 4 speed count */
SIO_REG(0xae, PWM_DC(50)), /* FAN[1] segment 5 speed count */
/*
* - FAN[1] follows PECI temperature;
* - FAN[1] duty will directly jump to the value of FAN1_SEG2;
* - FAN[1] duty will directly jump to the value of FAN1_SEG1;
* - enable the interpolation of the fan expect table;
* - [0,0,0]: 23.5 KHz;
*/
SIO_REG(0xaf, 0x1c),
SIO_REG(0xb3, 0x75), /* FAN[2] expect PWM duty */
SIO_REG(0xb6, 70), /* VT[2] boundary 1 temperature */
SIO_REG(0xb7, 65), /* VT[2] boundary 2 temperature */
SIO_REG(0xb8, 55), /* VT[2] boundary 3 temperature */
SIO_REG(0xb9, 45), /* VT[2] boundary 4 temperature */
SIO_REG(0xba, PWM_DC(100)), /* FAN[2] segment 1 speed count 0xff */
SIO_REG(0xbb, PWM_DC(85)), /* FAN[2] segment 2 speed count 0xd9 */
SIO_REG(0xbc, PWM_DC(70)), /* FAN[2] segment 3 speed count 0xb2 */
SIO_REG(0xbd, PWM_DC(60)), /* FAN[2] segment 4 speed count 0x99 */
SIO_REG(0xbe, PWM_DC(50)), /* FAN[2] segment 5 speed count 0x75 */
/*
* - FAN[2] follows PECI temperature;
* - FAN[2] duty will directly jump to the value of FAN2_SEG2;
* - FAN[2] duty will directly jump to the value of FAN2_SEG1;
* - enable the interpolation of the fan expect table;
* - [0,0,0]: 23.5 KHz;
*/
SIO_REG(0xbf, 0x1c),
};
static inline u8 sio_read(bool is_hwm, uint8_t idx)
{
return is_hwm ? pnp_read_hwm5_index(SIO_HWM_BASE, idx) : pnp_read_index(SIO_PORT, idx);
}
static inline void sio_write(bool is_hwm, uint8_t idx, uint8_t val)
{
is_hwm ? pnp_write_hwm5_index(SIO_HWM_BASE, idx, val) : pnp_write_index(SIO_PORT, idx, val);
}
static void sio_regs_setup(const struct sio_reg reg[], int size, bool is_hwm)
{
for (int i = 0; i < size; i++) {
uint8_t val = reg[i].val;
if (reg[i].extra_selector) {
val = sio_read(is_hwm, reg[i].idx);
val &= reg[i].mask;
val |= reg[i].val;
}
sio_write(is_hwm, reg[i].idx, val);
}
}
void mainboard_superio_init(void)
{
pnp_enter_conf_state(SIO_DEV(GLOBAL));
sio_regs_setup(ldn_reg_tbl, sizeof(ldn_reg_tbl)/sizeof(struct sio_reg), false);
pnp_exit_conf_state(SIO_DEV(GLOBAL));
sio_regs_setup(hwm_reg_tbl, sizeof(hwm_reg_tbl)/sizeof(struct sio_reg), true);
}