erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/rauru: Add 2nd source TAS2563 amps to support beep

Browse source 
Derive the audio amplifier from FW_CONFIG, and set up I2C and I2S for
TAS2563. Also pass the corresponding GPIO(s) to the payload.

TEST=build pass and driver init ok
BUG=b:357969183

Change-Id: I10cba7964d3847f2a74341b3130ff1e7bfd8d37a
Signed-off-by: Darren Ye <darren.ye@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85360
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit is contained in:
Jarried Lin 2024-11-28 18:22:41 +08:00 • committed by Yidi Lin
commit 4c8547704f
4 changed files with 54 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

17
src/mainboard/google/rauru/chromeos.c
View file

@ -2,6 +2,7 @@
#include <boot/coreboot_tables.h>
#include <drivers/tpm/cr50.h>
#include <fw_config.h>
#include <gpio.h>
#include "gpio.h"
@ -24,9 +25,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{ GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done" },
{ GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable" },
{ GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt" },
{ GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable" },
{ GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt" },
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
@ -37,6 +36,20 @@ void fill_lb_gpios(struct lb_gpios *gpios)
};
lb_add_gpios(gpios, sd_card_gpios, ARRAY_SIZE(sd_card_gpios));
}
struct lb_gpio nau8318_gpios[] = {
{GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"},
{GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable"},
};
struct lb_gpio smartamp_gpios[] = {
{GPIO_EN_SPKR.id, ACTIVE_LOW, -1, "speaker reset"},
};
if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_TAS2563)))
lb_add_gpios(gpios, smartamp_gpios, ARRAY_SIZE(smartamp_gpios));
else
lb_add_gpios(gpios, nau8318_gpios, ARRAY_SIZE(nau8318_gpios));
}
int cr50_plat_irq_status(void)

7
src/mainboard/google/rauru/devicetree.cb
View file

@ -1,5 +1,12 @@
## SPDX-License-Identifier: GPL-2.0-only
fw_config
field AUDIO_AMP 28 29
option AMP_NAU8318 0
option AMP_TAS2563 1
end
end
chip soc/mediatek/mt8196
device cpu_cluster 0 on end

4
src/mainboard/google/rauru/gpio.h
View file

@ -16,6 +16,10 @@
#define GPIO_AP_FP_FW_UP_STRAP GPIO(EINT27)
#define GPIO_EN_PWR_FP GPIO(PERIPHERAL_EN3)
#define GPIO_I2SI4_BCK GPIO(I2SIN1_BCK)
#define GPIO_I2SI4_LRCK GPIO(I2SIN1_LRCK)
#define GPIO_I2SO4_D0 GPIO(I2SOUT1_DO)
void setup_chromeos_gpios(void);
#endif

28
src/mainboard/google/rauru/mainboard.c
View file

@ -2,14 +2,41 @@
#include <console/console.h>
#include <device/device.h>
#include <fw_config.h>
#include <gpio.h>
#include <soc/addressmap.h>
#include <soc/bl31.h>
#include <soc/dpm_v2.h>
#include <soc/gpio_common.h>
#include <soc/i2c.h>
#include <soc/pcie.h>
#include <soc/usb.h>
#include "gpio.h"
#define AFE_SE_SECURE_CON1 (AUDIO_BASE + 0x5634)
static void configure_i2s(void)
{
/* Switch to normal mode */
write32p(AFE_SE_SECURE_CON1, 0x0);
/* SoC I2S */
gpio_set_mode(GPIO_I2SI4_BCK, GPIO_FUNC(I2SIN1_BCK, I2SIN4_BCK));
gpio_set_mode(GPIO_I2SI4_LRCK, GPIO_FUNC(I2SIN1_LRCK, I2SIN4_LRCK));
gpio_set_mode(GPIO_I2SO4_D0, GPIO_FUNC(I2SOUT1_DO, I2SOUT4_DATA0));
}
static void configure_audio(void)
{
if (fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_TAS2563))) {
mtk_i2c_bus_init(I2C3, I2C_SPEED_FAST);
configure_i2s();
}
printk(BIOS_INFO, "%s: done\n", __func__);
}
static void power_on_fpmcu(void)
{
/* Power on the fingerprint MCU */
@ -26,6 +53,7 @@ static void mainboard_init(struct device *dev)
{
setup_usb_host();
power_on_fpmcu();
configure_audio();
if (dpm_init())
printk(BIOS_ERR, "dpm init failed, DVFS may not work\n");