The LCD MIPI panel requires proper power-off commands before reset.
Skipping them may cause overpotential conditions, leading to image
stickiness or flicker.
On MTK platforms, CR50 reset is the only reboot path in coreboot.
Add mainboard_prepare_cr50_reset() implementation on skywalker to
power off the MIPI panel before issuing CR50 reset.
BUG=b:474187570
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=skywalker
Change-Id: I46a654e03ca2e7374cdaf05729f12b182669a64f
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91507
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Communication with GSC and EC is abnormal because Mica is
missing the following configurations: DRIVER_TPM_I2C_BUS,
EC_GOOGLE_CHROMEEC_SPI_BUS,and MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT.
BUG=b:489062509,b:489264026
TEST=build mica board, flash to Quenbi to verify the GSC and
EC communication functionality.
Check if there are any further abnormalities in the bootup log:
For GSC:
Probing TPM I2C: Cr50 TPM IRQ timeout!
For EC:
crosec_spi_io: Timeout waiting for framing byte.
Change-Id: I2ff158968f946eb780d593c8b1d1e8b07f95ce8a
Signed-off-by: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91517
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Device NVS is only used in southbridge code. Also move the platform.asl
file since it is mostly about southbridge stuff.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.
Change-Id: Ia0d301f6b77f7084a6d1dfe1238693c76c62ef7a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91401
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation to unify the Haswell and Broadwell codebases, move the
remaining Broadwell SoC code to the northbridge folder.
This change only moves the files, and does the minimal amount of edits
so that boards still build. Most of those edits boil down to "find and
replace".
Change-Id: I5bde032ee824a90328a78403ea03d39ad20f2b09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The PCH split was done many moons ago, in order to unify two codebases
with overlapping hardware support: Haswell + Lynx Point and Broadwell.
The on-package PCH found in Broadwell ULT/ULX CPUs is Wildcat Point.
This change only moves the files, and does the minimal amount of edits
so that boards still build. Most of those edits boil down to "find and
replace".
Change-Id: I29235b47970f81b5db6717801f2ab771ff980476
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91396
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 4c4bd3cd97 ("soc/intel/broadwell: Hook up PCI domain and CPU
cluster ops to devicetree") and commit 600fa266bd ("nb/intel/haswell:
Hook up PCI domain and CPU cluster ops to devicetree") decoupled the CPU
bus device operations from northbridge code. Since Haswell and Broadwell
both use the same CPU code, move the CPU bus ops to CPU code in order to
deduplicate them.
Change-Id: I11cbff3d87e233f40a40f2fc70840f6bf35b0cb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91463
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove explicit overrides for disable_c1_state_auto_demotion and
disable_package_c_state_demotion, reverting to the SoC default behavior
which allows the hardware to autonomously demote C1 and package
C-states.
BUG=b:455612673
TEST=Boot to OS on Google fatcat
Change-Id: Ica9348e668c64ac2b27f3970b23f963ba0a2e753
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Turn off Gen4 and Gen5 NVMe power at bootblock and turn on at romstage
to address device enumeration and link speed issues observed after power
cycles and warm/cold reboots. This change specifically resolves issues
seen with certain NVMe devices, particularly the Micron 3500, where
improper power sequencing can cause enumeration failures or incorrect
link speed negotiation.
BUG=none
TEST=Boot Fatcat board with Micron 3500 NVMe in Gen4/Gen5 M.2
slots. Perform multiple power cycles and warm/cold reboots. Verify
consistent NVMe enumeration and proper link speed using lspci output.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie929a3010acd74237d29a77c7582f1cae837a2e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91369
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This changes out the PRR0 named object for a method local variable
and avoids the use of a hardcoded offset
This solves the remark:
```
dsdt.asl 415: Name(PRR0, ResourceTemplate() {
Remark 2173 - ^ Creation of named objects within a method is highly inefficient, use globals or method local variables instead (\_SB.IQCR)
```
The IQCR function was tested, by evaluating it in the new
`dsdt.aml` file, as well as the old one with `acpiexec`:
`acpiexec -b "Evaluate _SB.IQCR $4bit_num_dec" dsdt.aml`,
where `$4bit_num_in_dec`, is a number between 0 and 15.
Expected output:
```
Evaluation of \_SB.IQCR returned object 0x5648f23cedd0, external buffer length 28
[Buffer] Length 0B = 0000: 89 06 00 09 01 $4bit_num_hex 00 00 00 79 00 // .........y.
```
Change-Id: I007d6b8df4eef4e8cb13cef45b95da7659d62cef
Signed-off-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The ADSP I2C initialization for charger/fuel-gauge is needed in both
normal boot and the off-mode/low-battery charging path. This patch
moves it before the conditional mainboard initialization skip, so it
runs in all cases.
BUG=b:436391478
TEST=Able to build and boot google/bluey.
Change-Id: I7a5c4e9c2a066a2ae43d57a87902528c93faecc5
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91365
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With proper staged M.2 slot power sequencing in place, remove the
root-port detect-timeout overrides and the StarBook ADL PCI hot-plug
CFR option.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50820c776011508f4d6bfa7053e827d7c53700b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90994
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable STARLABS_NVME_POWER_SEQUENCE and provide staged GPIO pad
configuration for the SSD slot (PWREN, PERST#, CLKREQ#).
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I22f1f8786db38b2720c544748cef58eb7259f239
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90991
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide staged GPIO pad configuration for the M.2 NVMe SSD and the
(discrete) M.2 2230 wireless module on supported StarBook variants.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6b3b607e73a2b1c437349f31cc6faaf662365da7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Implement Fatcat-style 3-stage M.2 NVMe slot sequencing
(PWREN, PERST#, CLKREQ#) for StarFighter and apply it to
all NVMe-capable ports (both Gen3 and Gen4).
This addresses intermittent NVMe detection problems on
cold/warm boot and improves PCIe link speed negotiation
by ensuring the device is held in reset with clocks gated
until slot power is enabled and coreboot is about to
initialize devices.
Sequence per NVMe port:
1) pre-mem: disable CLKREQ#, assert PERST#, PWREN=0
2) BS_PRE_DEVICE exit: PWREN=1, enable CLKREQ# native,
keep PERST# asserted
3) BS_DEV_INIT_CHIPS entry: deassert PERST#
Also update the variant gpio_table defaults so PWREN stays
off and CLKREQ# stays disconnected until the sequencing
code enables them.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic34e9e755e167e301348fbe7c75649401300f53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90974
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a shared helper (behind Kconfig) that owns the ramstage bootstate
ordering for the Star Labs NVMe/M.2 slot power sequence (PWREN, PERST#,
CLKREQ#).
Boards/variants provide pad configs for stage 2 and stage 3 either by
implementing the `variant_nvme_power_sequence_*()` helpers or by
providing pad tables via `variant_nvme_power_sequence_pads()` and
`variant_nvme_power_sequence_post_pads()`.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3d518c35c26f3d3ee1dd72b4a35861d19cdb85ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90973
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove CMOS option tables and defaults from Star Labs boards now that
EC state is persisted through EFI variable store options.
Drop remaining Merlin EC CMOS plumbing (RTC reads and ACPI fields) and
read settings only via the option backend.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cc7f6240adc4b396912d566c7de176d4d2cb92b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a Device NVS (DNVS) protocol and SMM handler to let ACPI read and
write a restricted set of coreboot options stored in the UEFI variable
store.
ACPI fills DNVS and triggers an SMI via APM_CNT (0xB2). SMM performs
the requested operation and updates DNVS with status and, for reads,
the returned value.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ice0ac36f6d0e1de88daf7010cb1771453547619e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91303
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because GPP_B05 is not required for EC or ISH interrupts,
it should be set to NC in coreboot to minimize power impact.
BUG=b:475879711
TEST=Build and boot to OS.
Change-Id: Ic56e16ca89968c8e2204d1609812f1d8d3548512
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The charging debug access port was previously only configured during
slow battery charging. Move this configuration into a dedicated
function, configure_charging_debug_access(), and call it within the
common mainboard_init() path.
This ensures the debug access port is consistently configured during
mainboard initialization, following the same pattern as parallel
charging.
BUG=b:488143407
TEST=Build Bluey/Quartz
Change-Id: Idacffd61834e0700619b240dfe362f3be90badb9
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91505
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Currently, mainboards that do not support Google TPM must manually
define stubs for chromeos_device_branded_plus_hard() and
chromeos_device_branded_plus_soft() to satisfy the linker.
Move these stubs into vendorcode/google/chromeos/chromeos.h as static
inline functions when CONFIG(TPM_GOOGLE) is disabled. This reduces
code duplication and allows the removal of redundant stub definitions
in the ptlrvp mainboard.
Change-Id: If270d4815c687a409fec7058c224f987f9e2741a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91474
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce EC_GOOGLE_CHROMEEC_LED_CONTROL to allow boards to opt-in to
manual LED/lightbar synchronization. This ensures that the AP firmware
can coordinate the lightbar state with boot animations or specific
power states (like critical battery alerts) without forcing the logic
on all ChromeEC-based platforms.
On Bluey, the lightbar logic is refactored into a helper function
`platform_init_lightbar()` to improve readability and is now gated
by the new Kconfig. Similar gating is applied to Fatcat's romstage.
Summary of changes:
- Add EC_GOOGLE_CHROMEEC_LED_CONTROL Kconfig option.
- Bluey: Refactor lightbar init into a helper and gate by Kconfig.
- Fatcat: Gate early lightbar initialization by Kconfig.
Change-Id: I6b0294b73b8b9929a6be0e15bf64f7e688b7da8c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add launch_charger_applet() to handle the system state when booting
in off-mode charging or low-power modes with a charger present.
Key features:
1. Monitoring: Periodically checks battery current (I-current) via
SPMI/PMIC registers.
2. Event Handling: Detects and clears EC power button and lid events.
If a manual power-on event is detected, the system triggers a
full board reset to ensure a clean boot to the OS (preventing
firmware state conflicts like ADSP-lite vs ADSP).
3. Shutdown: If the charger is removed, it signals the EC via
off-mode heartbeat and initiates an AP power-off.
BUG=b:439819922
BRANCH=None
TEST=Verified that the device enters the charging loop when plugged
in while off, and transitions to a full boot when the power button
is pressed.
Change-Id: I152f71eac89f5b522ea7b286517724e213c31e9a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91485
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename the PL4 powercap Kconfig symbol to MB_STARLABS_PL4_WATTS
and update the common powercap logic to use the namespaced
option.
Change-Id: If36d087accc13a03eac4715948a4ca47bd70c3c4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91461
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the BOARD_STARLABS_LITE_ADL preprocessor hook with a
weak baseboard function and provide the StarLite-specific SSDT
generator from the i5 variant directory.
Change-Id: Iea1a27fe1bf86bf970bd7021135760d8a1bc75a1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91460
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All Star Labs ADL boards select SOC_INTEL_COMMON_BLOCK_ASPM, so the
additional preprocessor guard in the PCIe CFR form is redundant.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id7cd4911666c02f88a9c1c5f074ac996744be23d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91459
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the i5 variant-specific CFR callbacks out of the baseboard
CFR menu and compile them from the variant directory. This
reduces preprocessor usage in the common file.
Change-Id: Ic03ec18aed100a95d347c49c2b1deecf1c3fd961
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Move StarLite Mk V (Lite ADL) into the ADL grouping under
src/mainboard/starlabs/adl/.
Like StarBook Horizon, keep common code in the ADL directory and place
model-specific data under src/mainboard/starlabs/adl/variants/ using the
SKU-style variant directory (i5).
Update MAINBOARD_DIR and related paths so binary blobs, SPD data and
CMOS layout continue to resolve correctly, and update documentation to
reflect the new blobs path.
Note that BUILD_TIMELESS ROM hashes change since MAINBOARD_DIR is
embedded in the CBFS config file.
BUG=None
TEST=BUILD_TIMELESS=1 build STARLABS_LITE_ADL
Change-Id: Ib367bc65ad63e848d9e20e7d55f542f135b3c1d5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91256
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the Star Labs Byte (Mk II / Mk III) into the ADL grouping under
src/mainboard/starlabs/adl/.
Like StarBook Horizon, model differences live under
src/mainboard/starlabs/adl/variants/ using SKU-style variant directories
to share common configuration. Byte Mk II (ADL) and Byte Mk III (TWL)
share a single "y2" variant directory.
Update MAINBOARD_DIR and CMOS layout handling so binary blob paths and
NVRAM options continue to resolve correctly.
Update the documentation to reflect the new blobs path.
Note that BUILD_TIMELESS ROM hashes change since MAINBOARD_DIR is
embedded in the CBFS config file.
BUG=None
TEST=BUILD_TIMELESS=1 build STARLABS_BYTE_ADL
Change-Id: I4b6be115a4ab2316d5ca4cc8e656e3643518273e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91255
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the card reader USB port, along with ACPI driver info
and the CFR option to control it.
Change-Id: I30dd26438f0a7b355061a45b9ffb7f447c89a751
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set the default power profile to Performance, regardless of whether
there is a fan present.
Change-Id: Id1d624355f9f08b5abb154e26026e70675322ddb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As the card reader isn't on a dedicated USB interface for all variants
for the StarLite, default to disable to ensure that an unused USB port
isn't enabled.
Change-Id: I2176fd6556797e468012c98f7e482b9573b5e3f7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The m920q and m720q are the same board, so rename the m920q to reflect
that
Change-Id: Ieef22530207ad4c35ac3cb4255d2ad65e62b65bf
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90374
Reviewed-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Convert the hybrid graphics mux into a generic device and give it an
alias so that the driver can reference it by name.
Change-Id: Icbf6f298cab9e11acc9363daba68f9fbc613e79d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Both models are quite similar, so reuse existing code and reduce
code duplication.
TEST=TIMELESS build shows identical devicetree.cb, DSDT, cmos layout,
bootblock, romstage and postcar stages. ramstage shows minor
differences as static.c is now build before hda_verb.c, resulting
in different location of data symbols. Binary analysis shows that
the data itself didn't change, just the position in the final
binary.
Change-Id: I2e7cf67c9e2542a199b11257e7349a55e0518aac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use the same GEN_DEC ranges as on t430. This makes the code look more
similar, but doesn't change the functionality. It changes the TIMELESS
build artifact.
Change-Id: Ibfac61f615fba2b91101125a2187b45af6dadd19
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91283
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the T430 look like the T530 codebase by reordering includes,
update the ACPI code and update the CMOS defaults file. Should have
not influence on functionality, but changes the TIMELESS build artifacts.
Change-Id: I2c300ecbf44fa950183ee5e05ba1e05cdf5ff00d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The pin widgets for the internal speakers and microphone should not
have the presence detect flag set, as this causes the jack detect
to fail on some distros, leading to headphone output not working.
TEST=build/boot LINK
Change-Id: I798d0cc4a0f4de65ebe51f1dafaeeb12728d2f40
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update the Creative CA0132 Pin Widget Verb Table from raw hex config
values to AZALIA_PIN_DESC for NIDs 0x0B–0x13, and use
AZALIA_PIN_CFG_NC(0) for N/C pins (0x0C–0x0F).
Mapping generated by hda-decoder utility.
TEST=build/boot LINK
Change-Id: Ia1c9bce2bf0a71aa3a60678828cbc6bc55f7bfc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add Micron MT62F1G32D2DS-020 WT:D as id 1, and add Micron
MT62F2G32D4DS-020 WT:D as id 0, resulting in the list below:
DRAM Part Name ID to assign
H58G66CK8BX147 0 (0000)
K3KL9L90EM-MGCU 0 (0000)
MT62F2G32D4DS-023 WT:C 0 (0000)
H58G56CK8BX146 1 (0001)
K3KL8L80EM-MGCU 1 (0001)
MT62F1G32D2DS-023 WT:C 1 (0001)
K3KLALA0EM-MGCU 2 (0010)
MT62F1G32D2DS-020 WT:D 1 (0001)
MT62F2G32D4DS-020 WT:D 0 (0000)
BUG=b:488228474
TEST=emerge-fatcat coreboot, rework by EE
flash it and boot normal.
Change-Id: I23ee56fe7e8f2e2ade75eaaf1fa19b91e784030f
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We found that the lotso project has already used
variant_is_half_populated. If we continue to use the
mb_get_channel_disable_mask API, it will reduce the memory of each DDR
by half. In reality, we are reducing the number of DDR modules (from 4
to 2), so we should remove mb_get_channel_disable_mask to ensure proper
DIMM identification.
BUG=b:468889066
BRANCH=None
TEST=boot to kernel success, and the log shows that the RAM ID is correct.
Change-Id: Ia7fc4610b3257bc20a871080f52f02e089b8531c
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Commit eb504eb49a ("mb/samsung/lumpy: Fix HDA pin configuration
issues") incorrectly used AZALIA_PIN_CFG_NC(0) as a standalone entry
for NID 0x08. Change to AZALIA_PIN_CFG(0, 0x08, AZALIA_PIN_CFG_NC(0))
so the verb for NID 0x08 is emitted correctly.
Change-Id: Iaf23b6e8791a352758189d92ad9c89414fc5a22d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
