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mb/starlabs: Drop PCIe detect-timeout/hotplug workarounds

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With proper staged M.2 slot power sequencing in place, remove the
root-port detect-timeout overrides and the StarBook ADL PCI hot-plug
CFR option.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50820c776011508f4d6bfa7053e827d7c53700b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90994
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2026-01-29 12:09:35 +00:00
commit 61c69ebfa8
9 changed files with 0 additions and 25 deletions
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1
src/mainboard/starlabs/adl/variants/i5/devicetree.cb
View file

@ -199,7 +199,6 @@ chip soc/intel/alderlake
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_detect_timeout_ms = 50,
}"
smbios_slot_desc "SlotTypeM2Socket3"

1
src/mainboard/starlabs/adl/variants/y2/devicetree.cb
View file

@ -189,7 +189,6 @@ chip soc/intel/alderlake
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_detect_timeout_ms = 50,
}"
smbios_slot_desc "SlotTypePciExpressGen3X4"
"SlotLengthLong"

8
src/mainboard/starlabs/common/include/common/cfr.h
View file

@ -91,14 +91,6 @@ static const struct sm_object microphone = SM_DECLARE_BOOL({
.default_value = true,
});
static const struct sm_object pci_hot_plug = SM_DECLARE_BOOL({
.opt_name = "pci_hot_plug",
.ui_name = "Third-Party SSD Support",
.ui_helptext = "Enables PCI Hot Plug, which slows down the SSD initialization. It"
" is required for certain third-party SSDs to be detected.",
.default_value = false,
});
static const struct sm_object power_profile = SM_DECLARE_ENUM({
.opt_name = "power_profile",
.ui_name = "Power Profile",

3
src/mainboard/starlabs/starbook/cfr.c
View file

@ -50,9 +50,6 @@ static struct sm_obj_form io_expansion_group = {
.ui_name = "I/O / Expansion",
.obj_list = (const struct sm_object *[]) {
&card_reader,
#if CONFIG(BOARD_STARLABS_STARBOOK_ADL)
&pci_hot_plug,
#endif
#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
&thunderbolt,
#endif

1
src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
View file

@ -199,7 +199,6 @@ chip soc/intel/alderlake
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_detect_timeout_ms = 50,
}"
smbios_slot_desc "SlotTypeM2Socket3"

8
src/mainboard/starlabs/starbook/variants/adl/ramstage.c
View file

@ -1,17 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <option.h>
#include <soc/ramstage.h>
#include <common/pin_mux.h>
void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
{
configure_pin_mux(supd);
/*
* Enable Hot Plug on RP5 to slow down coreboot so that
* third-party drives are detected.
*/
if (get_uint_option("pci_hot_plug", 0) == 1)
supd->PcieRpHotPlug[8] = 1;
}

1
src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
View file

@ -184,7 +184,6 @@ chip soc/intel/alderlake
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_detect_timeout_ms = 50,
}"
smbios_slot_desc "SlotTypeM2Socket3"

1
src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
View file

@ -250,7 +250,6 @@ chip soc/intel/meteorlake
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_detect_timeout_ms = 15,
}"
smbios_slot_desc "SlotTypeM2Socket3"

1
src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
View file

@ -253,7 +253,6 @@ chip soc/intel/alderlake
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_detect_timeout_ms = 50,
}"
smbios_slot_desc "SlotTypeM2Socket3"