Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.
BUG=b:391612392
TEST=Run suspend_stress_test on lisbon and verify that the device
suspends to S0ix.
Change-Id: I124b63061650c85ed84324f3e1558a583a1875e0
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.
BUG=b:391612392
TEST=Run suspend_stress_test on Bujia and verify that the device
suspends to S0ix.
Change-Id: Idee14e7d4df0a9cf8b06b33a52016c1b9228e459
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
GPP_H08 and GPP_H09 are configured in the bootblock, so remove the
configuration in ramstage to allow the serial output in ramstage.
Change-Id: I4b813370cf259fb1ca138dd1922c16f801b40cc4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Generate a new TME key will cause S3 exit to fail, so
don't do it.
Change-Id: Ie19cb7f11ad633405a9fc3c1faf1c3cc53113f51
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The Fn key on felino emits a scancode of 94 (0x5e).
BUG=b:395822961
TEST=Flash Felino, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: I297cc3dea577acff6c85804ba1f7e5778fc63736
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86613
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow boards to disable TME (total memory encryption) by guarding
selection of TME_KEY_REGENERATION_ON_WARM_BOOT on INTEL_TME.
This way, boards can set INTEL_TME to n in their Kconfig without
generating an unmet dependencies error.
The default behavior/Kconfig selections are unmodified with this change.
Change-Id: I0df1437798e7cafa228ca0e5ae0c32eff774ed09
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86621
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces the Intel Panther Lake (PTL) Reference Validation
Platform (RVP) mainboard definition. It is aligned with the Google
Fatcat mainboard in the coreboot codebase, with the commit hash
e2ea7f22c6.
Intel's proprietary platform, commonly referred to as PTLRVP, and
Google's Fatcat mainboard share a considerable degree of similarity in
their design and capabilities. Nevertheless, Intel faces unique
challenges and requires specific board configurations that Google does
not. Consequently, there is a necessity for a specialized mainboard
tailored to Intel's individual needs.
To maintain consistency with the Fatcat board definition, the Chrome OS
Board Information (CBI) firmware configuration aligns with that of
Google Fatcat. If necessary, new bits will be appended, starting from
the end of the 32-bit firmware configuration field.
BUG=b:398880064
TEST=The Intel PTLRVP board successfully boots to the operating System.
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84564
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
As was pointed out in comments on CB:83422 [0], the code lacks overflow
checks:
- when computing size of capsules in a single capsule block
- when computing size of capsules in all capsule blocks
If an overflow is triggered, the code might allocate a capsule buffer
smaller than the data that's going to be written to it leading to
overwriting memory after the buffer.
[0]: https://review.coreboot.org/c/coreboot/+/83422
Change-Id: I43d17d77197fc2cbd721d47941101551603c352a
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84541
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These lines are not needed because this mainboard does not have
an integrated display to control.
Tested on HP Pro 3400 Series.
Change-Id: Id39cd18713cc596eb2c92e028dad480fe7de8ef2
Signed-off-by: Vesek <venda.straka@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85847
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pro_3500_series was converted to a variant to include the Pro 3400, so rename the corresponding documentation.
Change-Id: I5977f223d6f004a801e163397d1c97febd7ee1d4
Signed-off-by: Vesek <venda.straka@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85846
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on autoport and HP Pro 3500.
As part of this change renamed 3500 to 3x00 and added this as
it's variant.
It's an almost identical board to the 3500 but has a smaller flash.
Other differences between boards were identified by autoport.
They may or may not important but were included anyway.
Tested on HP Pro 3400, behaves exactly as 3500 described in the docs.
Changes were not significant enough to require retesting on 3500.
Change-Id: I833996f6eddcaac91fb0ad0cd95fcc2a99447387
Signed-off-by: Vesek <venda.straka@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move SSD enable/reset pins to romstage to have more time for initialization.
BUG=b:398070426
BRANCH=None
TEST=Build francka and do EC reset to check the SSD boots to OS successfully
Change-Id: I468ba34a54046ef6ed3d5ec4c625a87bb5255640
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86593
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Recent PI releases have been distributing the ucode patch files as sbin
files instead of bin files. The sbin uses a 256 byte amd_fw_header to
wrap the bin file.
Offset 0x14 of the header is the size field. The can be extracted with
od to get the size of the ucode bin file. The bin file can then be
extracted with dd and placed in the build directory for inclusion as a
cbfs file.
In the case where both an sbin and bin ucode file are present, the bin
file will be added and a note will print at the start of the build about
the sbin file being skipped.
TEST=builds with only bin, only sbin, non-matching bin and sbin,
matching bin and sbin files
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I29768ea19543bdc76662e687f59bf31b76f555ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68122
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
QEMU has a maximum of 512 of emulated harts supported.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I149c8d8a43733c8ba3e02a84b0a3606d98f8b2c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Carlos López <carlos.lopezr4096@gmail.com>
The previous approach would increase the delay time by 50 ms. So move
WWAN power sequence to GPIO control to reduce boot time caused by WWAN
initialization. Additionally, add a 150ms delay to T0_OFF_MS before powering off the WWAN. This ensures that the WWAN Power OFF Sequence operates correctly during a reboot.
BUG=b:383212261
BRANCH=firmware-trulo-15217.771.B
TEST=Confirm the measured WWAN power sequence
Change-Id: Ie01019eca7eaa4bbb34dd80aeb65b9b6b08587fd
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86514
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Before I got the following error:
[ERROR] DDR5 speed of 3750 MHz is out of range
tested: glinda based mainboard
Change-Id: I141f63c4fc505a9e16eed132a9a550441f4ad68d
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86543
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Naresh Solanki <naresh.solanki@9elements.com>
Adds PAD_CFG_GPI_APIC_DRIVER macros to configure interrupt pad with
driver mode. This is needed when a PAD is configured as an interrupt
such that the corresponding GPI_IS status bit can be updated by the
host controller hardware.
BUG=none
TEST=Check a GPIO pad that is used as interrupt via GpioInt in the ACPI
device _CRS method and check the interrupt has been assigned in
/proc/interrupts.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ibc1ed3089c24302bc7eb02318714b8ec464fad01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86414
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PS0 and PS3 methods that return the Bluetooth power
resource. This allows the OS to turn on or off the device.
This fixes and issue where the Bluetooth reported a power
failure in device manager.
Change-Id: I0e37fc0369b1dc2b166f851daa183b145a09eb32
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86507
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
_PR3 should return resources required for the device to be in D3Hot
for which the Intel Bluetooth needs none, so remove it.
Change-Id: I65f206899affd46d791c2ba39235a1af320395d2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86595
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't attempt any GPIO operations of there isn't a reset
GPIO specified.
Change-Id: I9c97963e61f790f2d9c55d8ec1a384a5779782b4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86401
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Whilst the GPIO's used for Intel Bluetooth should always be consistent
as to whether they're active high or active low, adjust the driver to
pass the GPIO as a pointer, so that it can correctly account for
polarity.
Change-Id: Ib481d49d536b702fef149af882209501c61de6da
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The Intel reference code for Thunder Peak increase the reset delay
to 160ms from 105ms seen on Jefferson Peak, Cyclone Peak and others.
For the sake of 110ms, use 160ms to cover all use cases.
Change-Id: I19c1bf7eeffa340e2564381a184ebfaca89bf364
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Specify an enable GPIO for CNVi wireless so that the driver will
add support for WiFi SW RF Kill.
Test=boot starlite_adl/byte_adl, and use acpi_call dkms to check
that _OFF and _ON Methods in the power resource successfully
disable the wireless.
Change-Id: Ib172230f2c9e926870e35f040ce1b80628561863
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Check for the existence of BTRK method before attempting to
call it, as coreboot doesn't enforce its creation.
Change-Id: Ibb0dace635c6a014ce65ae3d1c96a92ff991ce5b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Hook CNVC and CNVS Methods into the power resource for the CNVi
which is provided via the `wifi/generic` driver to allow for WiFi
SW RF Kill (low power mode) support.
Add corresponding _PS3 and _PS0 Methods, change the power resource
to S0 from S5, and rename the power resource from WRST to CNVP for
better relevance.
Test=boot `starlabs/starlite_adl`, disconnect wireless and verify
with inteltool that the WIFI_RF_KILL GPIO is asserted.
Change-Id: I22292ad97c439e50fe5d7a6b79f77847e71ca62c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add two new methods, CNVS and CNVC, that can check and control
the enable GPIO for a CNVi module.
These will be used by the common code for WiFi SW RF Kill (Low
Power Mode).
Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is required when using 96GB of memory.
Change-Id: I3a2a3e737eeb9282a4edf09eb0a24019ceeb016e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86623
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The schematic is the same as Glassway project and only difference for CPU.
Therefore, we clone the coreboot settings of glassway to guren
then remove some configurations to meet those keypart/design for guren.
BUG=b:397149037
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.
Change-Id: Ia43a78c340426069571172319be1675b3d94eba4
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
For adding missing \n, find all potential missings by below script
and apply manual checks and fixes.
grep -nE "(DEBUG|ERROR)\(\".+[^\\n]\"" util/cbfstool/ -r
For using __func__ in debug message, below script is used with
manual checks and fixes.
grep -nE "DEBUG\(.+:" util/cbfstool/ -r
Change-Id: I3e2c225dc16a65470f9f94db89d8ec3711e781c8
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86567
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Upload the initial devicetree for meliks.
All devices and port usages are the same as pirrha, just copied from
pirrha's devicetree for the initial configuration except
typec_aux_bias_pads[0] since pirrha had incorrect setting.
About detection method of the touch screen device, the panel-built-in
touch screen for meliks needs some delay after panel power up, so it
may not be detected in coreboot phase. So we would keep `probed`
instead of `detect` for this special touch screen device to avoid
missing it in OS.
BUG=b:394359785
BRANCH=nissa
TEST=FW_NAME=meliks emerge-nissa coreboot
Change-Id: Ifd6dfbeca7276dbacd72f9145ed7119566c8faef
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86377
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.
- K3KL6L60GM-MGCT (Samsung)
- MT62F512M32D2DR-031 WT:B (Micron)
- K3KL8L80DM-MGCU (Samsung)
BUG=b:394359785
TEST=Build coreboot and verified booting to depthcharge
Change-Id: Ief1272ef4cb7971c3abfe6ee982b019121f54793
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86375
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Support oem_variables and change based on EC notify event.
BUG=b:394177292
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot
Change-Id: Iac18cb968906a9dfe53836432ba8dbefee1dcc8e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86394
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table. For Panther Lake, remove "Die Management Unit (DMU)
load completed" and add "ESE completed AUnit loading" instead.
990:CSME ROM started execution 0
992:ESE completed AUnit loading 0
944:CSE sent 'Boot Stall Done' to PMC 174,000
945:CSE started to handle ICC configuration 274,000 (100,000)
946:CSE sent 'Host BIOS Prep Done' to PMC 274,000 (0)
947:CSE received 'CPU Reset Done Ack sent' from PMC 448,000 (174,000)
0:1st timestamp 556,874 (108,874)
BUG=b:376218080
TEST=Able to see TS elapse prior to IA reset on Fatcat
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84872
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code compiles and works fine in x86_64. Thus allow the user
to use x86_64.
TEST: Booted on amd/birman+ to OS using EDK2 as payload.
Change-Id: If1b5d91a376770c0f0e1a4ee46dd625b401fbfa6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
On AMD platforms the SPI flash can be accessed using the ROM3
mapping in upper MMIO space. To reach the MMIO window the default
page tables must be extended to cover the address by default.
Add support for a SoC specific default address space being used on
x86_64, where the default of 4GiB/512GiB remains.
The size can be specified by the Kconfig CPU_PT_ROM_MAP_GB option.
Used in the following patch to use ROM3 mapping on AMD platforms.
TEST: Access ROM3 bar at 0xfd00000000 on amd/birman+ using x86_64
TEST: x86_64 still works on qemu/q35.
Change-Id: If669426f2b5ae40dd5c62e17f3a0234783b7d462
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Currently, coreboot tries to manually probe the memory for
the Spike target as part of the SOC_UCB_RISCV target.
However, Spike already passes a pointer to the device tree,
so use it instead to get the memory size (like qemu-riscv does).
TEST=Compile for SPIKE-RISCV and run (cmdline: spike -m1024 build/coreboot.elf)
Change-Id: I5c826ab5e4896e07a78632d5d594377a3d6a7a43
Signed-off-by: joel.bueno <joel.bueno@openchip.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86588
Reviewed-by: Carlos López <carlos.lopezr4096@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Because the AGAH EC code is based on monitoring adapter current to
choose the corresponding DPTF OEM variable table, but not every
project follows this design. Based on the comment below, the AGAH
EC code was removed in 2023, so remove the AGAH DPTF OEM variant,
allowing each OEM to adjust in EC ASL accordingly.
BUG=b:394177292
BRANCH=None
TEST=None
Change-Id: I2929eaa65a518b06f32e33cc31ae4a01bcfb77e8
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86493
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the newer verb for the ALC2669-VB6 from `starbook/mtl`,
as the current verb table failed to detect headphones being
connected.
Change-Id: Iaa50c6622f3ca75fbeff96300e08eb00e071c8b6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Use already defined macros in <spd.h> and <dram/ddr3.h>.
TEST=Built purism/librem_bdw (Librem 13 v1) with BUILD_TIMELESS=1, no
change in output ROM.
Change-Id: Id38b97017b43f1421129fed0bb9c1fff5c3423d8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82315
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI _PRT method was missing from PEG (SoC PCI-E) links, resulting in
OS complaining about interrupt routing:
pcieport 0000:00:06.0: can't derive routing for PCI INT A
Tested on `starbook_adl` with Ubuntu 24.04 by running SSD
benchmark with GNOME disks and suspend.
Change-Id: I2e36cee37716d3b003b9ce250f28fdf5581a15bc
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The Fn key on pujjoniru emits a scancode of 94 (0x5e).
BUG=b:398943428
TEST=Flash Pujjoniru, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: I8eb7f253a637741b0aa45aac4d1d59bd0309d559
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
According to the circuit schematic diagram, pujjoniru uses GPP_E17
as a write-protected gpio,so it is necessary to add the GPIO_PCH_WP
definition for GPP_E17 in gpio.h.
Duo to cros_gpios under variants/baseboard/nissa/gpio.c will call
GPIO_PCH_WP under variants/baseboard/nissa/include/baseboard/gpio.h,
causing our modifications to not take effect.
In order to achieve the above modification, we follow brya, we
modify DECLARE_CROS_GPIOS in variants/baseboard/nissa/gpio.c to
DECLARE_WEAK_CROS_GPIOS, so that the cros_gpios we defined in
/pujjoniru/gpio.c can overwrite variants/baseboard/nissa/gpio.c
BUG=b:396594296
TEST=wp status update verified by toggling it on and off.
Change-Id: Ic92ff33a5fde50a1a400043b2daba0414eb9e255
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86554
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
