mb/google/nissa/var/pujjoniru: Modify the gpio of GPIO_PCH_WP

According to the circuit schematic diagram, pujjoniru uses GPP_E17
as a write-protected gpio,so it is necessary to add the GPIO_PCH_WP
definition for GPP_E17 in gpio.h.

Duo to cros_gpios under variants/baseboard/nissa/gpio.c will call
GPIO_PCH_WP under variants/baseboard/nissa/include/baseboard/gpio.h,
causing our modifications to not take effect.

In order to achieve the above modification, we follow brya, we
modify DECLARE_CROS_GPIOS in variants/baseboard/nissa/gpio.c to
DECLARE_WEAK_CROS_GPIOS, so that the cros_gpios we defined in
/pujjoniru/gpio.c can overwrite variants/baseboard/nissa/gpio.c

BUG=b:396594296
TEST=wp status update verified by toggling it on and off.

Change-Id: Ic92ff33a5fde50a1a400043b2daba0414eb9e255
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86554
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/mainboard/google/brya/variants/baseboard/nissa/gpio.c

@@ -453,7 +453,7 @@ static const struct cros_gpio cros_gpios[] = {
 	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 };
-DECLARE_CROS_GPIOS(cros_gpios);
+DECLARE_WEAK_CROS_GPIOS(cros_gpios);
 
 const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
 {

src/mainboard/google/brya/variants/pujjoniru/gpio.c

@@ -1,9 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <baseboard/gpio.h>
+#include <variant/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
 #include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Pad configuration in ramstage */
 static const struct pad_config override_gpio_table[] = {
@@ -72,6 +73,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_NF_LOCK(GPP_E12, NONE, NF7, LOCK_CONFIG),
 	/* E13  : NC ==> GSPI1_SOC_MOSI_TCHSCR */
 	PAD_CFG_NF_LOCK(GPP_E13, NONE, NF7, LOCK_CONFIG),
+	/* E17 : THC0_SPI1_IO1 ==> SOC_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E17, NONE, LOCK_CONFIG),
 	/* E20 : DDP2_CTRLCLK ==> NC */
 	PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
 	/* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
@@ -201,3 +204,9 @@ const struct pad_config *variant_romstage_gpio_table(size_t *num)
 	*num = ARRAY_SIZE(romstage_gpio_table);
 	return romstage_gpio_table;
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+DECLARE_CROS_GPIOS(cros_gpios);

src/mainboard/google/brya/variants/pujjoniru/include/variant/gpio.h

@@ -3,6 +3,7 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
-#include <baseboard/gpio.h>
-
+#undef GPIO_PCH_WP
+/* WP signal to PCH */
+#define GPIO_PCH_WP		GPP_E17
 #endif