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mb/google/fatcat/var/francka: Adjust NVMe SSD power sequence

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Move SSD enable/reset pins to romstage to have more time for initialization.

BUG=b:398070426
BRANCH=None
TEST=Build francka and do EC reset to check the SSD boots to OS successfully

Change-Id: I468ba34a54046ef6ed3d5ec4c625a87bb5255640
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86593
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Frank Wu 2025-02-25 16:11:08 +08:00 • committed by Matt DeVillier
commit af2d11f963
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/fatcat/variants/francka/gpio.c
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@ -416,6 +416,8 @@ static const struct pad_config early_gpio_table[] = {
/* Pad configuration in romstage */
static const struct pad_config romstage_gpio_table[] = {
/* GPP_B16: SOC_SSD2_EN */
PAD_CFG_GPO(GPP_B16, 1, PLTRST),
/* GPP_C00: SOC_SMBCLK */
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
/* GPP_C01: SOC_SMBDATA */
@ -424,6 +426,8 @@ static const struct pad_config romstage_gpio_table[] = {
PAD_CFG_GPO(GPP_H03, 0, DEEP),
/* GPP_H17: FP_RST_1V8_OD# */
PAD_CFG_GPO(GPP_H17, 0, DEEP),
/* GPP_E03: SOC_SSD2_RST# */
PAD_CFG_GPO(GPP_E03, 1, PLTRST),
};
const struct pad_config *variant_gpio_table(size_t *num)