This adds a directory with files copied over from Jerry, in addition to
build system related changes (configs/* and Kconfig stuff) necessary
to emerge-veyron_brain coreboot.
The next patch will account for differences between Jerry and Brain.
BUG=none
BRANCH=none
TEST=emerge-veyron_brain coreboot works
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I972f2623d9b0a43e3ea5312b3c4cd34ab44edc36
Reviewed-on: https://chromium-review.googlesource.com/236989
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/242134
Tested-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
For coreboot Gus and Jaq are the same as mighty.
Copy from Mighty.
BUG=chrome-os-partner:35238
TEST=emerge coreboot
BRANCH=veyron
Change-Id: I7ec68401e6b053d54f8666b3d56d9da20e224605
Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/239475
Reviewed-by: Julius Werner <jwerner@chromium.org>
Essentially a copy of veyron_speedy for now.
BUG=chrome-os-partner:33269
TEST=build
Change-Id: Ib10fe9fd7337e197ba376b2e9be632b1ad83f74e
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/237413
Reviewed-by: Julius Werner <jwerner@chromium.org>
Call FspNotify to finish the platform initialization. Attempts to
load the payload.
BRANCH=none
BUG=None
TEST=Use the following steps to reproduce:
1. Get the private FSP parts
2. Copy configs/config.samus.fsp to configs/config.samus
3. If running on a non-samus board, in
src/mainboard/google/samus/Kconfig:
a. Comment out select EC_GOOGLE_CHROMEEC
b. Comment out select EC_SOFTWARE_SYNC
4. If running on a non-samus board, in
src/mainboard/google/samus/spd/spd.c comment out the check for
valid SPD data at the end of the file
5. Build and run on Samus
6. Test successful if the code attempts to load the payload
Change-Id: I007bd5481e532e14dca3f158b8eb1d8cb4dc3f47
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/232874
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Repartition the RAM initialization code to share the setup and caching
support. Display the parameters for the MemoryInit call. Initialize
memory using the FSP binary. Upon return display the HOBs and memory
configuration before hanging displaying POST code 0x35.
BRANCH=none
BUG=None
TEST=Use the following steps to reproduce:
1. Get the private FSP parts
2. Copy configs/config.samus.fsp to configs/config.samus
3. Build and run on Samus
4. After power on, POST code should be 0x35 if successful, hangs in
src/soc/intel/broadwell/romstage/romstage.c/romstage_common
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Change-Id: I02e1ea422644da1f6285812dd36045a70e0f4324
Reviewed-on: https://chromium-review.googlesource.com/231285
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
During execution, src/soc/intel/broadwell/romstage/fsp_1_1.inc calls
src/soc/intel/fsp/fsp_util.c/find_fsp, added in change list 229573,
to locate the FSP binary in CBFS. Determine the TempRamInit entry point
and call TempRamInit. After returning, fsp_1_1.inc calls into
src/soc/intel/broadwell/romstage/romstage.c/romstage_main.
BRANCH=none
BUG=None
TEST=Use the following steps to reproduce:
1. Get the private FSP parts: internal 187295
2. Copy configs/config.samus.fsp to configs/config.samus
3. Build and run on Samus
4. After power on, POST code should be 0x35 if successful, hangs in
src/soc/intel/broadwell/romstage/romstage.c/romstage_main
Change-Id: Id7d17b7b46e73a7b6b4dae6ee859016dab6e6d6f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/234140
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Essentially a copy of veyron_jerry for now
BUG=chrome-os-partner:33269
TEST=emerge-veyron_speedy coreboot
BRANCH=None
Change-Id: Ife457db4fd67fe69bcd4082694b3372eccfb304b
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/233822
Reviewed-by: Julius Werner <jwerner@chromium.org>
Turn on CBMEM console support now that we have all the pieces in place,
and also (re-)enable timestamps on Pinky (which have previously been
taken out of the config file there, but not on Jerry and Mighty).
BRANCH=None
BUG=None
TEST=Booted Pinky, confirmed 'cbmem -c' and 'cbmem -t' show correct
results (except for the dual init in the bootblock, which CL:231942
will take care of).
Change-Id: I424902f237537c9f1a65b9266a53e971ca25c09e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232616
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch fixes up our board configs to conform to the new relationship
between CBFS_SIZE and ROM_SIZE, and to remove the FLASHMAP_OFFSET which
now has a useful default.
BRANCH=None
BUG=None
TEST=Tested with other patches.
Change-Id: I4781df455ee15ddc91b51d2c42cdeedd60089027
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/231576
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The total bootprom size is 2MB, so coreboot should fit into
512KB. FMAP is placed in the depthcharde device tree definition at
0xe0000.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the appropriate chromeos-bmpblk and deptcharge changes,
chromeos-bootimage now builds successfully.
Change-Id: I5eb086a7529947e00cdee626e164b3328ff86ccb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/232238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is a (hopefully temporary) workaround for some bad panels
that do not work unless we have extra delay before running the
option rom.
BUG=chrome-os-partner:33671
BRANCH=samus
TEST=build and boot on samus with 'bad' panel and ensure that
the panel is always (50/50 times) brought up in developer and
recovery modes.
Change-Id: Ife779803c89ff56ff9b50e6b7c7c022300062a63
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228883
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This code change is trying to avoid system hang due to "no enough MTRRs"
This is based on https://chromium-review.googlesource.com/174653
BUG=chrome-os-partner:33417
BRANCH=None
TEST=compile ok, make sure MTRRs are enough for memory regions.
Check 4GiB memory usage by cat /proc/meminfo
Change-Id: Ide8177577314fddceaf20e14615b745d888b3743
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/226511
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
First phase of urara (runnig on FPGA board) can not support verified
boot, let's not enable it yet.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with this and poreceeding patches the Urara board builds again.
Change-Id: I9ecdae32a0372219686348cb0b314a2e825ecea3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
git add fwserial.auron_pearlvalley is missed in previous commit
So, it casue compile error when download new source code
BRANCH=none
BUG=None
TEST=re-download code, compile ok and boot OS
Change-Id: I40795415d0ff811bea1ac9427a98e34880efb8ac
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/224912
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This is essentially a copy of veyron_pinky for now.
BUG=chrome-os-partner:33269
TEST=build and boot
Change-Id: I0d473361e0850ee3b11da5a809f8396826ccdad6
Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/225301
This change is based on wtm2
BUG=none
BRANCH=none
TEST=compile ok and boot to OS
Change-Id: I9625662eaf782f44258c15b956d04cbfdb82a14a
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/212368
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This selects the correct custom vesa mode for Samus which is
added to the VBIOS for bitmaps to be scaled appropriately.
BUG=chrome-os-partner:32643
BRANCH=samus
TEST=build and boot on samus
Change-Id: Id2b3349340e85ab6f29374dff096c39ac0506fc6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222675
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This Kconfig option was removed with the memlayout patch.
BUG=None
TEST=None
Change-Id: Ie768202503b4d205a6911fe643367c62903a153d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219681
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Flashmap offset needs to be defined through
configuration option. This definition must match
the FMAP location defined the appropriate device
tree in the deptcharge repository.
BUG=chrome-os-partner:32152
TEST=attempts to look up VPD in flash map do not
fail anymore
Change-Id: I474f0c4854fc264bcae8eb27fbd43966a381aa91
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219440
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We retroactively decided to use the variant name "pinky" for the Rk3288
board we're currently bringing up, and retcon the unadorned "veyron"
name to refer to the Rockchip evaluation board. Since we currently have
no interest to maintain coreboot support for that board in our tree,
let's rename everything to "veyron_pinky" and forget about "veyron".
CQ-DEPEND=CL:217592
BUG=chrome-os-partner:30167
TEST='emerge-veyron libpayload coreboot' fails but
'emerge-veyron_pinky libpayload coreboot' succeeds.
Change-Id: I366391efc8e0a7c610584b50cea331a0164da6f3
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217674
Reviewed-by: David Hendricks <dhendrix@chromium.org>
revert this change will cause auron show ERROR
CBFS: ERROR: No file header found at 0x7ff480
and need to add skip ERROR while running suspend_stress_test
But we need to support diff CPU sku, so I revert this change
This reverts commit 5e11145fb3.
BUG=none
TEST=build ok, boot to OS
Change-Id: I29da779f9e0d9a3a8bae46c49250c769a18d0c10
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/216810
Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The VBIOS DID and the id in config file are inconsistent.
Without this commint, you will need to skip error during
suspend stress test
BUG=chrome-os-partner:31286
BRANCH=none
TEST=build ok, check no ERROR exists in log
Change-Id: Ia73cb4cc4f4b0844a0692f6e760bcc089d64d09c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/216172
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Removing BOOTROM_SDRAM_INIT from Ryu's config
allows the code in sdram.c to handle LPDDR3 init
for all 3 SDRAM vendors now.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BUILD=None
TEST=Built for rush and rush_ryu, booted Ryu to kernel
login AOK (w/Samsung LPDDR3). Booted Rush to where it
tried to load in the Ryu kernel (need to create Rush
boot media). Micron and Hynix SDRAM boards need test
(none here in AZ).
Change-Id: Ieaa880f955e546e707230ba34e09594410c5fd8a
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/215864
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This allows to build coreboot for the mips based board called urara.
BUG=chrome-os-partner:31438
TEST=emerge-urara coreboot succeeds with the proper coreboot image
created. No testing yet.
Change-Id: I420476802fb12e5d02f07998d6c01d8c38b7a83e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214659
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Switch from the haswell cpu/northbridge/southbridge interface
to the soc/intel/broadwell interface.
- Use new headers where appropriate
- Remove code that is now done by the SOC generic code
- Update GPIO map to drop LP specific handling
- Update INT15 handlers, drop all but the boot display hook
Auron port of Samus commit 715dbb06e9.
BUG=chrome-os-partner:31286
TEST=Compile only.
BRANCH=None.
Change-Id: Ie8a660dd139c382929485ff458b5945e8ad72d23
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213957
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
For some reason the veyron config file was checked in as a shell
executable. This patch removes the x bit.
BUG=none
TEST=the file is not executable any more:
$ ls -l configs/config.veyron
-rw-r--r-- 1 vbendeb eng 190 Aug 7 11:39 configs/config.veyron
Change-Id: I6314b58cd4477bc1b4dc44a2651a5f291c23707a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213157
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Add the supporting Kconfig options and infrastructure for
performing vboot firmware verification.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Built and ran on ryu into depthcharge noting vboot paths
being taken.
Change-Id: Ie4c8c3939990a12fc528423948b236230392eb7c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211134
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Most things still needs to be filled in, but this will allow us to build boards which use this SOC.
BUG=chrome-os-partner:29778
TEST=emerge-veyron coreboot
Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/205069
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Once LPDDR3 init is supported in the ryu romstage, this can
be reverted. Note that this 528MHz BCT has been pre-qualed
by NVIDIA AE's, but will be updated as more tuning is done.
BUG=none
BRANCH=none
TEST=Builds, BCT is in binary, but I have no HW here to test on
Change-Id: I315a9a5d56290bb5f51863b15053d2171db7b1e4
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/208384
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
The default CBFS size configuration setting is incorrect in case of
Qualcomm SOC targets, as the coreboot blob is much smaller than the
actual bootprom. Note that this size also must match the board fmap
defined in the appropriate depthcharge board directory.
BUG=chromium:394068
TEST=manual
. previously failing to boot coreboot image does not fail to load
depthcharge anymore.
Change-Id: I1b178970b1deee05705490542e4a0c57500379dd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/208146
Reviewed-by: David Hendricks <dhendrix@chromium.org>
In order to make sharing of the location of MTS microcode easier
provide a Kconfig option that is the path to the files.
BUG=chrome-os-partner:30569
BRANCH=None
TEST=Built rush coreboot.
Change-Id: I36775d0018fc8591d5e77c2943e28a51381713f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207839
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This is a clone of rush for the time being. All the incompatible
bits can be moved later.
BUG=chrome-os-partner:30569
BRANCH=None
TEST=Built coreboot for rush_ryu board
Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207838
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
