auron: Convert mainboard to use soc/intel/broadwell
Switch from the haswell cpu/northbridge/southbridge interface
to the soc/intel/broadwell interface.
- Use new headers where appropriate
- Remove code that is now done by the SOC generic code
- Update GPIO map to drop LP specific handling
- Update INT15 handlers, drop all but the boot display hook
Auron port of Samus commit 715dbb06e9.
BUG=chrome-os-partner:31286
TEST=Compile only.
BRANCH=None.
Change-Id: Ie8a660dd139c382929485ff458b5945e8ad72d23
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213957
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Shawn Nematbakhsh
chrome-internal-fetch
parent
f4e9c9b338
commit
ae51ac971e
16 changed files with 243 additions and 570 deletions
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@ -5,6 +5,8 @@ CONFIG_BOARD_GOOGLE_AURON=y
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CONFIG_HAVE_MRC=y
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CONFIG_MRC_FILE="/build/auron/firmware/mrc.bin"
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CONFIG_CBFS_SIZE=0x100000
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CONFIG_HAVE_REFCODE_BLOB=y
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CONFIG_REFCODE_BLOB_FILE="/build/auron/firmware/efi.elf"
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CONFIG_CONSOLE_CBMEM=y
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# CONFIG_CONSOLE_SERIAL is not set
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# CONFIG_PCI_ROM_RUN is not set
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@ -2,10 +2,7 @@ if BOARD_GOOGLE_AURON
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_HASWELL
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select SOUTHBRIDGE_INTEL_LYNXPOINT
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select INTEL_LYNXPOINT_LP
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select SOC_INTEL_BROADWELL
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select BOARD_ROMSIZE_KB_8192
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select EC_GOOGLE_CHROMEEC
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select EC_SOFTWARE_SYNC
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@ -21,12 +18,16 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select CACHE_ROM
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select MARK_GRAPHICS_MEM_WRCOMB
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select MONOTONIC_TIMER_MSR
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select CHROMEOS_RAMOOPS_DYNAMIC
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config VBOOT_RAMSTAGE_INDEX
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hex
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default 0x2
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config VBOOT_REFCODE_INDEX
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hex
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default 0x3
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config MAINBOARD_DIR
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string
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default google/auron
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@ -35,10 +36,6 @@ config MAINBOARD_PART_NUMBER
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string
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default "Auron"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config IRQ_SLOT_COUNT
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int
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default 18
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@ -18,6 +18,6 @@
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*/
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Name(OIPG, Package() {
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Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button
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Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect
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Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // no recovery button
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Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
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})
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@ -61,16 +61,6 @@ Scope (\_SB)
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})
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Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
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Method (_DSW, 3, NotSerialized)
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{
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Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
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If (LEqual (Arg0, 1)) {
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// Enable GPIO as wake source
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\_SB.PCI0.LPCB.GWAK (Local0)
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}
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}
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}
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Device (TSCR)
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@ -96,15 +86,5 @@ Scope (\_SB)
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})
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Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
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Method (_DSW, 3, NotSerialized)
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{
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Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
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If (LEqual (Arg0, 1)) {
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// Enable GPIO as wake source
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\_SB.PCI0.LPCB.GWAK (Local0)
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}
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}
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}
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}
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@ -68,19 +68,5 @@ Method(_PTS,1)
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Method(_WAK,1)
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{
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/* Update AC status */
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Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0)
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if (LNotEqual (Local0, \PWRS)) {
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Store (Local0, \PWRS)
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Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
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}
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/* Update LID status */
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Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0)
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if (LNotEqual (Local0, \LIDS)) {
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Store (Local0, \LIDS)
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Notify (\_SB.LID0, 0x80)
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}
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Return(Package(){0,0})
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}
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@ -21,20 +21,6 @@
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Scope (\_TZ)
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{
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// Handler for throttle requests on this platform
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// 0 = Stop throttling
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// 1 = Start throttling
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Method (THRT, 1, Serialized)
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{
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If (LEqual (Arg0, 0)) {
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/* Disable Power Limit */
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\_SB.PCI0.MCHC.CTLD ()
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} Else {
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/* Enable Power Limit */
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\_SB.PCI0.MCHC.CTLE (\F0PW)
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}
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}
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ThermalZone (THRM)
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{
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Name (_TC1, 0x02)
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@ -29,67 +29,29 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/msr.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <ec/google/chromeec/ec.h>
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#include <broadwell/acpi.h>
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#include <broadwell/nvs.h>
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#include "thermal.h"
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extern const unsigned char AmlCode[];
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <southbridge/intel/lynxpoint/nvs.h>
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#include "thermal.h"
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static void acpi_update_thermal_table(global_nvs_t *gnvs)
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{
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gnvs->tmps = TEMPERATURE_SENSOR_ID;
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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gnvs->tmax = MAX_TEMPERATURE;
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gnvs->f0pw = EC_THROTTLE_POWER_LIMIT;
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gnvs->flvl = 1;
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}
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static void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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gnvs->apic = 1;
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gnvs->mpen = 1; /* Enable Multi Processing */
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gnvs->pcnt = dev_count_cpu();
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acpi_init_gnvs(gnvs);
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/* Enable USB ports in S3 */
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gnvs->s3u0 = 1;
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gnvs->s3u1 = 1;
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/* Disable USB ports in S5 */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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/* CBMEM TOC */
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gnvs->cmem = 0;
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/* TPM Present */
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gnvs->tpmp = 1;
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/* IGD Displays */
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gnvs->ndid = 3;
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gnvs->did[0] = 0x80000100;
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gnvs->did[1] = 0x80000240;
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gnvs->did[2] = 0x80000410;
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gnvs->did[3] = 0x80000410;
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gnvs->did[4] = 0x00000005;
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#if CONFIG_CHROMEOS
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// TODO(reinauer) this could move elsewhere?
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chromeos_init_vboot(&(gnvs->chromeos));
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gnvs->chromeos.vbt2 = google_ec_running_ro() ?
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ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
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#endif
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/* Update the mem console pointer. */
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gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
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acpi_update_thermal_table(gnvs);
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gnvs->tmps = TEMPERATURE_SENSOR_ID;
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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gnvs->tmax = MAX_TEMPERATURE;
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}
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unsigned long acpi_fill_madt(unsigned long current)
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@ -101,13 +63,7 @@ unsigned long acpi_fill_madt(unsigned long current)
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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2, IO_APIC_ADDR, 0);
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/* INT_SRC_OVR */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 0);
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
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return current;
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return acpi_madt_irq_overrides(current);
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}
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unsigned long acpi_fill_ssdt_generator(unsigned long current,
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@ -119,13 +75,11 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current,
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unsigned long acpi_fill_slit(unsigned long current)
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{
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// Not implemented
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return current;
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}
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unsigned long acpi_fill_srat(unsigned long current)
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{
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/* No NUMA, no SRAT */
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return current;
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}
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@ -142,9 +96,6 @@ unsigned long write_acpi_tables(unsigned long start)
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acpi_mcfg_t *mcfg;
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acpi_fadt_t *fadt;
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acpi_facs_t *facs;
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#if CONFIG_HAVE_ACPI_SLIC
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acpi_header_t *slic;
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#endif
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acpi_header_t *ssdt;
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acpi_header_t *dsdt;
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global_nvs_t *gnvs;
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@ -255,15 +206,7 @@ unsigned long write_acpi_tables(unsigned long start)
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dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
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printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
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dsdt->length);
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#if CONFIG_HAVE_ACPI_SLIC
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printk(BIOS_DEBUG, "ACPI: * SLIC\n");
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slic = (acpi_header_t *)current;
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current += acpi_create_slic(current);
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ALIGN_CURRENT;
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acpi_add_table(rsdp, slic);
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#endif
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dsdt->length);
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printk(BIOS_DEBUG, "ACPI: * SSDT\n");
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ssdt = (acpi_header_t *)current;
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@ -272,13 +215,6 @@ unsigned long write_acpi_tables(unsigned long start)
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acpi_add_table(rsdp, ssdt);
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ALIGN_CURRENT;
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printk(BIOS_DEBUG, "ACPI: * SSDT2\n");
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ssdt = (acpi_header_t *)current;
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acpi_create_serialio_ssdt(ssdt);
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current += ssdt->length;
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acpi_add_table(rsdp, ssdt);
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ALIGN_CURRENT;
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printk(BIOS_DEBUG, "current = %lx\n", current);
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printk(BIOS_INFO, "ACPI: done.\n");
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return current;
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@ -18,16 +18,14 @@
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*/
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#include <string.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#if CONFIG_EC_GOOGLE_CHROMEEC
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#include "ec.h"
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#include <console/console.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <ec/google/chromeec/ec.h>
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#endif
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#include <broadwell/gpio.h>
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#include "ec.h"
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/* SPI Write protect is GPIO 16 */
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#define CROS_WP_GPIO 58
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@ -39,13 +37,9 @@
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static int get_lid_switch(void)
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{
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#if CONFIG_EC_GOOGLE_CHROMEEC
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u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
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return !!(ec_switches & EC_SWITCH_LID_OPEN);
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#else
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return 0;
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#endif
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}
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static void fill_lb_gpio(struct lb_gpio *gpio, int num,
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@ -91,7 +85,6 @@ int get_developer_mode_switch(void)
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* the other is driven by Servo. */
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int get_recovery_mode_switch(void)
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{
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#if CONFIG_EC_GOOGLE_CHROMEEC
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u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
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u32 ec_events;
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@ -104,9 +97,6 @@ int get_recovery_mode_switch(void)
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return !!(ec_events &
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
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#else
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return 0;
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#endif
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}
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int get_write_protect_state(void)
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@ -1,4 +1,4 @@
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chip northbridge/intel/haswell
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chip soc/intel/broadwell
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# Enable eDP Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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@ -21,108 +21,85 @@ chip northbridge/intel/haswell
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register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
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register "pirqa_routing" = "0x8b"
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register "pirqb_routing" = "0x8a"
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register "pirqc_routing" = "0x8b"
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register "pirqd_routing" = "0x8b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x80"
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# EC range is 0x800-0x9ff
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x00fc0901"
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# EC_SMI is GPIO34
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register "alt_gp_smi_en" = "0x0004"
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register "gpe0_en_1" = "0x00000000"
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# EC_SCI is GPIO36
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register "gpe0_en_2" = "0x00000010"
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register "gpe0_en_3" = "0x00000000"
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register "gpe0_en_4" = "0x00000000"
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register "sata_port_map" = "0x1"
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register "sio_acpi_mode" = "0"
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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# Force enable ASPM for PCIe Port1
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register "pcie_port_force_aspm" = "0x01"
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# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013c0000"
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register "s0ix_enable" = "1"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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end
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chip cpu/intel/haswell
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E)
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register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S)
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register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E)
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register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S)
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end
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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device pci 03.0 on end # mini-hd audio
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chip southbridge/intel/lynxpoint
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register "pirqa_routing" = "0x8b"
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register "pirqb_routing" = "0x8a"
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register "pirqc_routing" = "0x8b"
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register "pirqd_routing" = "0x8b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x80"
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# EC range is 0x800-0x9ff
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x00fc0901"
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# EC_SMI is GPIO34
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register "alt_gp_smi_en" = "0x0004"
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register "gpe0_en_1" = "0x00000000"
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# EC_SCI is GPIO36
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register "gpe0_en_2" = "0x00000010"
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register "gpe0_en_3" = "0x00000000"
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register "gpe0_en_4" = "0x00000000"
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register "ide_legacy_combined" = "0x0"
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||||
register "sata_ahci" = "0x1"
|
||||
register "sata_port_map" = "0x1"
|
||||
|
||||
# DTLE DATA / EDGE values
|
||||
register "sata_port0_gen3_dtle" = "0x5"
|
||||
register "sata_port1_gen3_dtle" = "0x5"
|
||||
|
||||
register "sio_acpi_mode" = "0"
|
||||
register "sio_i2c0_voltage" = "0" # 3.3V
|
||||
register "sio_i2c1_voltage" = "0" # 3.3V
|
||||
|
||||
# Force enable ASPM for PCIe Port1
|
||||
register "pcie_port_force_aspm" = "0x01"
|
||||
|
||||
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
|
||||
register "icc_clock_disable" = "0x013c0000"
|
||||
|
||||
# Route all USB ports to XHCI per default
|
||||
register "xhci_default" = "1"
|
||||
|
||||
device pci 13.0 off end # Smart Sound Audio DSP
|
||||
device pci 14.0 on end # USB3 XHCI
|
||||
device pci 15.0 on end # Serial I/O DMA
|
||||
device pci 15.1 on end # I2C0
|
||||
device pci 15.2 on end # I2C1
|
||||
device pci 15.3 off end # GSPI0
|
||||
device pci 15.4 off end # GSPI1
|
||||
device pci 15.5 off end # UART0
|
||||
device pci 15.6 off end # UART1
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT
|
||||
device pci 17.0 off end # SDIO
|
||||
device pci 19.0 off end # GbE
|
||||
device pci 1b.0 on end # High Definition Audio
|
||||
device pci 1c.0 on end # PCIe Port #1
|
||||
device pci 1c.1 off end # PCIe Port #2
|
||||
device pci 1c.2 off end # PCIe Port #3
|
||||
device pci 1c.3 off end # PCIe Port #4
|
||||
device pci 1c.4 off end # PCIe Port #5
|
||||
device pci 1c.5 off end # PCIe Port #6
|
||||
device pci 1d.0 on end # USB2 EHCI
|
||||
device pci 1e.0 off end # PCI bridge
|
||||
device pci 1f.0 on
|
||||
chip ec/google/chromeec
|
||||
# We only have one init function that
|
||||
# we need to call to initialize the
|
||||
# keyboard part of the EC.
|
||||
device pnp ff.1 on # dummy address
|
||||
end
|
||||
device pci 13.0 off end # Smart Sound Audio DSP
|
||||
device pci 14.0 on end # USB3 XHCI
|
||||
device pci 15.0 on end # Serial I/O DMA
|
||||
device pci 15.1 on end # I2C0
|
||||
device pci 15.2 on end # I2C1
|
||||
device pci 15.3 off end # GSPI0
|
||||
device pci 15.4 off end # GSPI1
|
||||
device pci 15.5 off end # UART0
|
||||
device pci 15.6 off end # UART1
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT
|
||||
device pci 17.0 off end # SDIO
|
||||
device pci 19.0 off end # GbE
|
||||
device pci 1b.0 on end # High Definition Audio
|
||||
device pci 1c.0 on end # PCIe Port #1
|
||||
device pci 1c.1 off end # PCIe Port #2
|
||||
device pci 1c.2 off end # PCIe Port #3
|
||||
device pci 1c.3 off end # PCIe Port #4
|
||||
device pci 1c.4 off end # PCIe Port #5
|
||||
device pci 1c.5 off end # PCIe Port #6
|
||||
device pci 1d.0 on end # USB2 EHCI
|
||||
device pci 1e.0 off end # PCI bridge
|
||||
device pci 1f.0 on
|
||||
chip ec/google/chromeec
|
||||
# We only have one init function that
|
||||
# we need to call to initialize the
|
||||
# keyboard part of the EC.
|
||||
device pnp ff.1 on # dummy address
|
||||
end
|
||||
end # LPC bridge
|
||||
device pci 1f.2 on end # SATA Controller
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.6 on end # Thermal
|
||||
end
|
||||
end
|
||||
end # LPC bridge
|
||||
device pci 1f.2 on end # SATA Controller
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.6 on end # Thermal
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -31,22 +31,21 @@ DefinitionBlock(
|
|||
{
|
||||
// Some generic macros
|
||||
#include "acpi/platform.asl"
|
||||
#include "acpi/mainboard.asl"
|
||||
|
||||
// global NVS and variables
|
||||
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
|
||||
#include <soc/intel/broadwell/acpi/globalnvs.asl>
|
||||
|
||||
// General Purpose Events
|
||||
//#include "acpi/gpe.asl"
|
||||
|
||||
// CPU
|
||||
#include <cpu/intel/haswell/acpi/cpu.asl>
|
||||
#include <soc/intel/broadwell/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/haswell/acpi/haswell.asl>
|
||||
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
|
||||
#include <soc/intel/broadwell/acpi/systemagent.asl>
|
||||
#include <soc/intel/broadwell/acpi/pch.asl>
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -58,5 +57,8 @@ DefinitionBlock(
|
|||
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
|
||||
|
||||
// Chipset specific sleep states
|
||||
#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
|
||||
#include <soc/intel/broadwell/acpi/sleepstates.asl>
|
||||
|
||||
// Mainboard specific
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -18,20 +19,16 @@
|
|||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <device/pci.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <southbridge/intel/lynxpoint/pch.h>
|
||||
#include <broadwell/acpi.h>
|
||||
|
||||
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
||||
{
|
||||
acpi_header_t *header = &(fadt->header);
|
||||
u16 pmbase = get_pmbase();
|
||||
|
||||
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
|
||||
memcpy(header->signature, "FACP", 4);
|
||||
header->length = sizeof(acpi_fadt_t);
|
||||
header->revision = 3;
|
||||
header->revision = 5;
|
||||
memcpy(header->oem_id, OEM_ID, 6);
|
||||
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
|
||||
memcpy(header->asl_compiler_id, ASLC, 4);
|
||||
|
|
@ -42,114 +39,12 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
|||
fadt->model = 1;
|
||||
fadt->preferred_pm_profile = PM_MOBILE;
|
||||
|
||||
fadt->sci_int = 0x9;
|
||||
fadt->smi_cmd = APM_CNT;
|
||||
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
|
||||
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
|
||||
fadt->s4bios_req = 0x0;
|
||||
fadt->pstate_cnt = 0;
|
||||
|
||||
fadt->pm1a_evt_blk = pmbase;
|
||||
fadt->pm1b_evt_blk = 0x0;
|
||||
fadt->pm1a_cnt_blk = pmbase + 0x4;
|
||||
fadt->pm1b_cnt_blk = 0x0;
|
||||
fadt->pm2_cnt_blk = pmbase + 0x50;
|
||||
fadt->pm_tmr_blk = pmbase + 0x8;
|
||||
fadt->gpe0_blk = pmbase + 0x80;
|
||||
fadt->gpe1_blk = 0;
|
||||
|
||||
fadt->pm1_evt_len = 4;
|
||||
fadt->pm1_cnt_len = 2;
|
||||
fadt->pm2_cnt_len = 1;
|
||||
fadt->pm_tmr_len = 4;
|
||||
fadt->gpe0_blk_len = 32;
|
||||
fadt->gpe1_blk_len = 0;
|
||||
fadt->gpe1_base = 0;
|
||||
fadt->cst_cnt = 0;
|
||||
fadt->p_lvl2_lat = 1;
|
||||
fadt->p_lvl3_lat = 87;
|
||||
fadt->flush_size = 1024;
|
||||
fadt->flush_stride = 16;
|
||||
fadt->duty_offset = 1;
|
||||
fadt->duty_width = 0;
|
||||
fadt->day_alrm = 0xd;
|
||||
fadt->mon_alrm = 0x00;
|
||||
fadt->century = 0x00;
|
||||
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
|
||||
|
||||
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
|
||||
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
|
||||
ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
|
||||
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
|
||||
|
||||
fadt->reset_reg.space_id = 1;
|
||||
fadt->reset_reg.bit_width = 8;
|
||||
fadt->reset_reg.bit_offset = 0;
|
||||
fadt->reset_reg.resv = 0;
|
||||
fadt->reset_reg.addrl = 0xcf9;
|
||||
fadt->reset_reg.addrh = 0;
|
||||
|
||||
fadt->reset_value = 6;
|
||||
fadt->x_firmware_ctl_l = (unsigned long)facs;
|
||||
fadt->x_firmware_ctl_h = 0;
|
||||
fadt->x_dsdt_l = (unsigned long)dsdt;
|
||||
fadt->x_dsdt_h = 0;
|
||||
|
||||
fadt->x_pm1a_evt_blk.space_id = 1;
|
||||
fadt->x_pm1a_evt_blk.bit_width = 32;
|
||||
fadt->x_pm1a_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_evt_blk.resv = 0;
|
||||
fadt->x_pm1a_evt_blk.addrl = pmbase;
|
||||
fadt->x_pm1a_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_evt_blk.space_id = 1;
|
||||
fadt->x_pm1b_evt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_evt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_evt_blk.resv = 0;
|
||||
fadt->x_pm1b_evt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_evt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1a_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1a_cnt_blk.bit_width = 16;
|
||||
fadt->x_pm1a_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1a_cnt_blk.resv = 0;
|
||||
fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
|
||||
fadt->x_pm1a_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm1b_cnt_blk.space_id = 1;
|
||||
fadt->x_pm1b_cnt_blk.bit_width = 0;
|
||||
fadt->x_pm1b_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm1b_cnt_blk.resv = 0;
|
||||
fadt->x_pm1b_cnt_blk.addrl = 0x0;
|
||||
fadt->x_pm1b_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm2_cnt_blk.space_id = 1;
|
||||
fadt->x_pm2_cnt_blk.bit_width = 8;
|
||||
fadt->x_pm2_cnt_blk.bit_offset = 0;
|
||||
fadt->x_pm2_cnt_blk.resv = 0;
|
||||
fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
|
||||
fadt->x_pm2_cnt_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_pm_tmr_blk.space_id = 1;
|
||||
fadt->x_pm_tmr_blk.bit_width = 32;
|
||||
fadt->x_pm_tmr_blk.bit_offset = 0;
|
||||
fadt->x_pm_tmr_blk.resv = 0;
|
||||
fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
|
||||
fadt->x_pm_tmr_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe0_blk.space_id = 0;
|
||||
fadt->x_gpe0_blk.bit_width = 0;
|
||||
fadt->x_gpe0_blk.bit_offset = 0;
|
||||
fadt->x_gpe0_blk.resv = 0;
|
||||
fadt->x_gpe0_blk.addrl = 0;
|
||||
fadt->x_gpe0_blk.addrh = 0x0;
|
||||
|
||||
fadt->x_gpe1_blk.space_id = 1;
|
||||
fadt->x_gpe1_blk.bit_width = 0;
|
||||
fadt->x_gpe1_blk.bit_offset = 0;
|
||||
fadt->x_gpe1_blk.resv = 0;
|
||||
fadt->x_gpe1_blk.addrl = 0x0;
|
||||
fadt->x_gpe1_blk.addrh = 0x0;
|
||||
acpi_fill_in_fadt(fadt);
|
||||
|
||||
header->checksum =
|
||||
acpi_checksum((void *) fadt, header->length);
|
||||
|
|
|
|||
|
|
@ -20,105 +20,105 @@
|
|||
#ifndef AURON_GPIO_H
|
||||
#define AURON_GPIO_H
|
||||
|
||||
struct pch_lp_gpio_map;
|
||||
#include <broadwell/gpio.h>
|
||||
|
||||
const struct pch_lp_gpio_map mainboard_gpio_map[] = {
|
||||
LP_GPIO_UNUSED, /* 0: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 1: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 2: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 3: UNUSED */
|
||||
LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
|
||||
LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
|
||||
LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
|
||||
LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
|
||||
LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */
|
||||
LP_GPIO_INPUT, /* 9: RAM_ID1 */
|
||||
LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
|
||||
LP_GPIO_UNUSED, /* 11: UNUSED */
|
||||
LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
|
||||
LP_GPIO_INPUT, /* 13: RAM_ID0 */
|
||||
LP_GPIO_INPUT, /* 14: EC_IN_RW */
|
||||
LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
|
||||
LP_GPIO_UNUSED, /* 16: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 17: UNUSED */
|
||||
LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
|
||||
LP_GPIO_UNUSED, /* 19: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 20: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 21: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 22: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 23: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 24: UNUSED */
|
||||
LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
|
||||
LP_GPIO_UNUSED, /* 26: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 27: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 28: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 29: UNUSED */
|
||||
LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
|
||||
LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
|
||||
LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
|
||||
LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
|
||||
LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
|
||||
LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
|
||||
LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
|
||||
LP_GPIO_UNUSED, /* 37: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 38: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 39: UNUSED */
|
||||
LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
|
||||
LP_GPIO_UNUSED, /* 41: UNUSED */
|
||||
LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
|
||||
LP_GPIO_UNUSED, /* 43: UNUSED */
|
||||
LP_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
|
||||
LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
|
||||
LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
|
||||
LP_GPIO_INPUT, /* 47: RAM_ID2 */
|
||||
LP_GPIO_UNUSED, /* 48: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 49: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 50: UNUSED */
|
||||
LP_GPIO_INPUT, /* 51: ALS_INT_L */
|
||||
LP_GPIO_INPUT, /* 52: SIM_DET */
|
||||
LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
|
||||
LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
|
||||
LP_GPIO_UNUSED, /* 55: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 56: UNUSED */
|
||||
LP_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
|
||||
LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
|
||||
LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
|
||||
LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
|
||||
LP_GPIO_UNUSED, /* 61: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 62: UNUSED */
|
||||
LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
|
||||
LP_GPIO_UNUSED, /* 64: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 65: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
|
||||
LP_GPIO_UNUSED, /* 67: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 68: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 69: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 70: UNUSED */
|
||||
LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
|
||||
LP_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
|
||||
LP_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
|
||||
LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
|
||||
LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
|
||||
LP_GPIO_UNUSED, /* 76: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 77: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 78: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 79: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 80: UNUSED */
|
||||
LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */
|
||||
LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
|
||||
LP_GPIO_UNUSED, /* 83: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 84: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 85: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
|
||||
LP_GPIO_UNUSED, /* 87: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 88: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 89: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 90: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 91: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 92: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 93: UNUSED */
|
||||
LP_GPIO_UNUSED, /* 94: UNUSED */
|
||||
LP_GPIO_END
|
||||
static const struct gpio_config mainboard_gpio_config[] = {
|
||||
PCH_GPIO_UNUSED, /* 0: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 1: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 2: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 3: UNUSED */
|
||||
PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */
|
||||
PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */
|
||||
PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */
|
||||
PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */
|
||||
PCH_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */
|
||||
PCH_GPIO_INPUT, /* 9: RAM_ID1 */
|
||||
PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */
|
||||
PCH_GPIO_UNUSED, /* 11: UNUSED */
|
||||
PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */
|
||||
PCH_GPIO_INPUT, /* 13: RAM_ID0 */
|
||||
PCH_GPIO_INPUT, /* 14: EC_IN_RW */
|
||||
PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */
|
||||
PCH_GPIO_UNUSED, /* 16: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 17: UNUSED */
|
||||
PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */
|
||||
PCH_GPIO_UNUSED, /* 19: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 20: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 21: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 22: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 23: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 24: UNUSED */
|
||||
PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */
|
||||
PCH_GPIO_UNUSED, /* 26: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 27: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 28: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 29: UNUSED */
|
||||
PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */
|
||||
PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */
|
||||
PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */
|
||||
PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */
|
||||
PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */
|
||||
PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
|
||||
PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */
|
||||
PCH_GPIO_UNUSED, /* 37: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 38: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 39: UNUSED */
|
||||
PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */
|
||||
PCH_GPIO_UNUSED, /* 41: UNUSED */
|
||||
PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */
|
||||
PCH_GPIO_UNUSED, /* 43: UNUSED */
|
||||
PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */
|
||||
PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */
|
||||
PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */
|
||||
PCH_GPIO_INPUT, /* 47: RAM_ID2 */
|
||||
PCH_GPIO_UNUSED, /* 48: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 49: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 50: UNUSED */
|
||||
PCH_GPIO_INPUT, /* 51: ALS_INT_L */
|
||||
PCH_GPIO_INPUT, /* 52: SIM_DET */
|
||||
PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */
|
||||
PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */
|
||||
PCH_GPIO_UNUSED, /* 55: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 56: UNUSED */
|
||||
PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */
|
||||
PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */
|
||||
PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */
|
||||
PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */
|
||||
PCH_GPIO_UNUSED, /* 61: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 62: UNUSED */
|
||||
PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */
|
||||
PCH_GPIO_UNUSED, /* 64: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 65: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */
|
||||
PCH_GPIO_UNUSED, /* 67: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 68: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 69: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 70: UNUSED */
|
||||
PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */
|
||||
PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */
|
||||
PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */
|
||||
PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */
|
||||
PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */
|
||||
PCH_GPIO_UNUSED, /* 76: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 77: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 78: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 79: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 80: UNUSED */
|
||||
PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */
|
||||
PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */
|
||||
PCH_GPIO_UNUSED, /* 83: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 84: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 85: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */
|
||||
PCH_GPIO_UNUSED, /* 87: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 88: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 89: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 90: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 91: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 92: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 93: UNUSED */
|
||||
PCH_GPIO_UNUSED, /* 94: UNUSED */
|
||||
PCH_GPIO_END
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -35,16 +35,9 @@
|
|||
#include <arch/interrupt.h>
|
||||
#include <boot/coreboot_tables.h>
|
||||
#include "hda_verb.h"
|
||||
#include <southbridge/intel/lynxpoint/pch.h>
|
||||
#include "ec.h"
|
||||
#include "onboard.h"
|
||||
|
||||
void mainboard_suspend_resume(void)
|
||||
{
|
||||
/* Call SMM finalize() handlers before resume */
|
||||
outb(0xcb, 0xb2);
|
||||
}
|
||||
|
||||
#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN
|
||||
static int int15_handler(void)
|
||||
{
|
||||
|
|
@ -54,32 +47,20 @@ static int int15_handler(void)
|
|||
__func__, X86_AX, X86_BX, X86_CX, X86_DX);
|
||||
|
||||
switch (X86_AX) {
|
||||
case 0x5f34:
|
||||
/*
|
||||
* Set Panel Fitting Hook:
|
||||
* bit 2 = Graphics Stretching
|
||||
* bit 1 = Text Stretching
|
||||
* bit 0 = Centering (do not set with bit1 or bit2)
|
||||
* 0 = video bios default
|
||||
*/
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0001;
|
||||
res = 1;
|
||||
break;
|
||||
case 0x5f35:
|
||||
/*
|
||||
* Boot Display Device Hook:
|
||||
* bit 0 = CRT
|
||||
* bit 1 = TV (eDP) *
|
||||
* bit 2 = EFP *
|
||||
* bit 1 = RESERVED
|
||||
* bit 2 = EFP
|
||||
* bit 3 = LFP
|
||||
* bit 4 = CRT2
|
||||
* bit 5 = TV2 (eDP) *
|
||||
* bit 6 = EFP2 *
|
||||
* bit 7 = LFP2
|
||||
* bit 4 = RESERVED
|
||||
* bit 5 = EFP3
|
||||
* bit 6 = EFP2
|
||||
* bit 7 = RESERVED
|
||||
*/
|
||||
X86_AX = 0x005f;
|
||||
X86_CX = 0x0000;
|
||||
X86_CX = 0x0008;
|
||||
res = 1;
|
||||
break;
|
||||
case 0x5f51:
|
||||
|
|
|
|||
|
|
@ -18,75 +18,35 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <cbfs.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/intel/haswell/haswell.h>
|
||||
#include <northbridge/intel/haswell/haswell.h>
|
||||
#include <northbridge/intel/haswell/raminit.h>
|
||||
#include <southbridge/intel/lynxpoint/pch.h>
|
||||
#include <southbridge/intel/lynxpoint/lp_gpio.h>
|
||||
#include "gpio.h"
|
||||
#include <string.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <broadwell/gpio.h>
|
||||
#include <broadwell/pei_data.h>
|
||||
#include <broadwell/pei_wrapper.h>
|
||||
#include <broadwell/romstage.h>
|
||||
#include "spd.h"
|
||||
#include "gpio.h"
|
||||
|
||||
const struct rcba_config_instruction rcba_config[] = {
|
||||
|
||||
/*
|
||||
* GFX INTA -> PIRQA (MSI)
|
||||
* D28IP_P1IP PCIE INTA -> PIRQA
|
||||
* D29IP_E1P EHCI INTA -> PIRQD
|
||||
* D20IP_XHCI XHCI INTA -> PIRQC (MSI)
|
||||
* D31IP_SIP SATA INTA -> PIRQF (MSI)
|
||||
* D31IP_SMIP SMBUS INTB -> PIRQG
|
||||
* D31IP_TTIP THRT INTC -> PIRQA
|
||||
* D27IP_ZIP HDA INTA -> PIRQG (MSI)
|
||||
*/
|
||||
|
||||
/* Device interrupt pin register (board specific) */
|
||||
RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
|
||||
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
|
||||
RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
|
||||
RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
|
||||
(INTB << D28IP_P4IP)),
|
||||
RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
|
||||
RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
|
||||
RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
|
||||
RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
|
||||
|
||||
/* Device interrupt route registers */
|
||||
RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
|
||||
RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
|
||||
RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
|
||||
RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
|
||||
RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
|
||||
RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
|
||||
RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
|
||||
RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
|
||||
|
||||
/* Disable unused devices (board specific) */
|
||||
RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
|
||||
|
||||
RCBA_END_CONFIG,
|
||||
};
|
||||
|
||||
void mainboard_romstage_entry(unsigned long bist)
|
||||
void mainboard_romstage_entry(struct romstage_params *rp)
|
||||
{
|
||||
struct pei_data pei_data;
|
||||
|
||||
struct romstage_params romstage_params = {
|
||||
.pei_data = &pei_data,
|
||||
.gpio_map = &mainboard_gpio_map,
|
||||
.rcba_config = &rcba_config[0],
|
||||
.bist = bist,
|
||||
};
|
||||
post_code(0x32);
|
||||
|
||||
/* Fill out PEI data */
|
||||
/* Ensure the EC is in the right mode for recovery */
|
||||
google_chromeec_early_init();
|
||||
|
||||
/* Initialize GPIOs */
|
||||
init_gpios(mainboard_gpio_config);
|
||||
|
||||
/* Fill out PEI DATA */
|
||||
memset(&pei_data, 0, sizeof(pei_data));
|
||||
mainboard_fill_pei_data(&pei_data);
|
||||
mainboard_fill_spd_data(&pei_data);
|
||||
rp->pei_data = &pei_data;
|
||||
|
||||
/* Call into the real romstage main with this board's attributes. */
|
||||
romstage_common(&romstage_params);
|
||||
romstage_common(rp);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -21,15 +21,15 @@
|
|||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <southbridge/intel/lynxpoint/nvs.h>
|
||||
#include <southbridge/intel/lynxpoint/pch.h>
|
||||
#include <southbridge/intel/lynxpoint/me.h>
|
||||
#include <northbridge/intel/haswell/haswell.h>
|
||||
#include <cpu/intel/haswell/haswell.h>
|
||||
#include <broadwell/pm.h>
|
||||
#include <broadwell/smm.h>
|
||||
#include <elog.h>
|
||||
|
||||
/* Include EC functions */
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <broadwell/gpio.h>
|
||||
#include <broadwell/iomap.h>
|
||||
#include <broadwell/nvs.h>
|
||||
#include <broadwell/pm.h>
|
||||
#include <broadwell/smm.h>
|
||||
#include "ec.h"
|
||||
|
||||
/* Codec enable: GPIO45 */
|
||||
|
|
@ -74,9 +74,9 @@ static u8 mainboard_smi_ec(void)
|
|||
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
|
||||
|
||||
/* Go to S5 */
|
||||
pm1_cnt = inl(get_pmbase() + PM1_CNT);
|
||||
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
|
||||
pm1_cnt |= (0xf << 10);
|
||||
outl(pm1_cnt, get_pmbase() + PM1_CNT);
|
||||
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -98,12 +98,12 @@ void mainboard_smi_sleep(u8 slp_typ)
|
|||
/* Disable USB charging if required */
|
||||
switch (slp_typ) {
|
||||
case 3:
|
||||
if (smm_get_gnvs()->s3u0 == 0)
|
||||
if (smm_get_gnvs()->s3u0 == 0) {
|
||||
google_chromeec_set_usb_charge_mode(
|
||||
0, USB_CHARGE_MODE_DISABLED);
|
||||
if (smm_get_gnvs()->s3u1 == 0)
|
||||
google_chromeec_set_usb_charge_mode(
|
||||
1, USB_CHARGE_MODE_DISABLED);
|
||||
}
|
||||
|
||||
set_gpio(GPIO_PP3300_CODEC_EN, 0);
|
||||
set_gpio(GPIO_WLAN_DISABLE_L, 0);
|
||||
|
|
@ -112,12 +112,12 @@ void mainboard_smi_sleep(u8 slp_typ)
|
|||
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
|
||||
break;
|
||||
case 5:
|
||||
if (smm_get_gnvs()->s5u0 == 0)
|
||||
if (smm_get_gnvs()->s5u0 == 0) {
|
||||
google_chromeec_set_usb_charge_mode(
|
||||
0, USB_CHARGE_MODE_DISABLED);
|
||||
if (smm_get_gnvs()->s5u1 == 0)
|
||||
google_chromeec_set_usb_charge_mode(
|
||||
1, USB_CHARGE_MODE_DISABLED);
|
||||
}
|
||||
|
||||
set_gpio(GPIO_PP3300_CODEC_EN, 0);
|
||||
set_gpio(GPIO_WLAN_DISABLE_L, 0);
|
||||
|
|
@ -136,25 +136,9 @@ void mainboard_smi_sleep(u8 slp_typ)
|
|||
;
|
||||
}
|
||||
|
||||
#define APMC_FINALIZE 0xcb
|
||||
|
||||
static int mainboard_finalized = 0;
|
||||
|
||||
int mainboard_smi_apmc(u8 apmc)
|
||||
{
|
||||
switch (apmc) {
|
||||
case APMC_FINALIZE:
|
||||
if (mainboard_finalized) {
|
||||
printk(BIOS_DEBUG, "SMI#: Already finalized\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
intel_pch_finalize_smm();
|
||||
intel_northbridge_haswell_finalize_smm();
|
||||
intel_cpu_haswell_finalize_smm();
|
||||
|
||||
mainboard_finalized = 1;
|
||||
break;
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
google_chromeec_set_smi_mask(0);
|
||||
/* Clear all pending events */
|
||||
|
|
|
|||
|
|
@ -22,9 +22,6 @@
|
|||
|
||||
#define TEMPERATURE_SENSOR_ID 0 /* PECI */
|
||||
|
||||
/* Power level to set when EC requests throttle */
|
||||
#define EC_THROTTLE_POWER_LIMIT 12 /* 12W */
|
||||
|
||||
/* Temperature which OS will shutdown at */
|
||||
#define CRITICAL_TEMPERATURE 99
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue