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auron: Mainboard code cleanup

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Remove unneeded configs + board version selection logic, and make minor
style changes.

BUG=chrome-os-partner:31286
TEST=Compile only.
BRANCH=None.

Change-Id: I715793a580e86d69a8c07fd2905b2336bd6b031f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213951
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Shawn Nematbakhsh 2014-08-21 10:57:52 -07:00 • committed by chrome-internal-fetch
commit 983c99b6d1
4 changed files with 14 additions and 32 deletions
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4
configs/config.auron
View file

@ -34,7 +34,3 @@ CONFIG_VBOOT_VERIFY_FIRMWARE=y
CONFIG_FLASHMAP_OFFSET=0x00610000
# CONFIG_MULTIBOOT is not set
CONFIG_PAYLOAD_NONE=y
CONFIG_MAINBOARD_VENDOR="Acer"
CONFIG_SUBSYSTEM_VENDOR_ID=0x1025
CONFIG_SUBSYSTEM_DEVICE_ID=0x0a11
CONFIG_LOCK_MANAGEMENT_ENGINE=y

7
src/mainboard/google/auron/chromeos.c
View file

@ -29,6 +29,9 @@
#include <ec/google/chromeec/ec.h>
#endif
/* SPI Write protect is GPIO 16 */
#define CROS_WP_GPIO 58
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
@ -66,7 +69,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
gpios->count = GPIO_COUNT;
gpio = gpios->gpios;
fill_lb_gpio(gpio++, 58, ACTIVE_HIGH, "write protect", 0);
fill_lb_gpio(gpio++, CROS_WP_GPIO, ACTIVE_HIGH, "write protect", 0);
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery",
get_recovery_mode_switch());
fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",
@ -108,5 +111,5 @@ int get_recovery_mode_switch(void)
int get_write_protect_state(void)
{
return get_gpio(58);
return get_gpio(CROS_WP_GPIO);
}

3
src/mainboard/google/auron/onboard.h
View file

@ -37,7 +37,4 @@
#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a
#define AURON_BOARD_VERSION_PROTO 0
#define AURON_BOARD_VERSION_EVT 1
#endif

32
src/mainboard/google/auron/romstage.c
View file

@ -18,20 +18,17 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <delay.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <cbfs.h>
#include <console/console.h>
#include "cpu/intel/haswell/haswell.h"
#include "ec/google/chromeec/ec.h"
#include "northbridge/intel/haswell/haswell.h"
#include "northbridge/intel/haswell/raminit.h"
#include "southbridge/intel/lynxpoint/pch.h"
#include "southbridge/intel/lynxpoint/lp_gpio.h"
#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include "gpio.h"
#include "onboard.h"
const struct rcba_config_instruction rcba_config[] = {
@ -85,21 +82,10 @@ static void copy_spd(struct pei_data *peid)
if (!spd_file)
die("SPD data not found.");
switch (google_chromeec_get_board_version()) {
case AURON_BOARD_VERSION_PROTO:
/* Index 0 is 2GB config with CH0 only. */
if (spd_index == 0)
peid->dimm_channel1_disabled = 3;
break;
case AURON_BOARD_VERSION_EVT:
default:
/* Index 0-2 are 4GB config with both CH0 and CH1.
* Index 4-6 are 2GB config with CH0 only. */
if (spd_index > 3)
peid->dimm_channel1_disabled = 3;
break;
}
/* Index 0-2 are 4GB config with both CH0 and CH1.
* Index 4-6 are 2GB config with CH0 only. */
if (spd_index > 3)
peid->dimm_channel1_disabled = 3;
if (ntohl(spd_file->len) <
((spd_index + 1) * sizeof(peid->spd_data[0]))) {