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rk3288: Use timestamp region for pre-cbmem timestamps

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BUG=None
BRANCH=None
TEST=Compiles successfully for veyron_pinky

Change-Id: I3862e9bf2c32085c921adae4c1dcdf88ff0f3ff3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/227243
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Furquan Shaikh 2014-11-03 14:39:11 -08:00 • committed by chrome-internal-fetch
commit 0fabdbb058
6 changed files with 22 additions and 46 deletions
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1
configs/config.veyron_pinky
View file

@ -2,7 +2,6 @@ CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_GOOGLE_VEYRON_PINKY=y
CONFIG_COREBOOT_ROMSIZE_KB_1024=y
# CONFIG_CONSOLE_SERIAL is not set
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_ELOG=y
# CONFIG_CONSOLE_CBMEM=y
CONFIG_FLASHMAP_OFFSET=0x00100000

27
src/mainboard/google/veyron_jerry/romstage.c
View file

@ -79,13 +79,8 @@ static void configure_l2ctlr(void)
void main(void)
{
void *entry;
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t start_romstage_time;
uint64_t before_dram_time;
uint64_t after_dram_time;
uint64_t base_time = timestamp_get();
start_romstage_time = timestamp_get();
#endif
timestamp_add_now(TS_START_ROMSTAGE);
console_init();
configure_l2ctlr();
@ -93,13 +88,9 @@ void main(void)
/* vdd_log 1200mv is enough for ddr run 666Mhz */
regulate_vdd_log(1200);
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = timestamp_get();
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_init(get_sdram_config());
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = timestamp_get();
#endif
timestamp_add_now(TS_AFTER_INITRAM);
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
mmu_config_range((uintptr_t)_dram/MiB,
@ -108,20 +99,14 @@ void main(void)
_dma_coherent_size/MiB, DCACHE_OFF);
cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
timestamp_add(TS_AFTER_INITRAM, after_dram_time);
#endif
entry = vboot2_load_ramstage();
if (entry == NULL) {
timestamp_add(TS_START_COPYRAM, timestamp_get());
timestamp_add_now(TS_START_COPYRAM);
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
CONFIG_CBFS_PREFIX "/ramstage");
timestamp_add(TS_END_COPYRAM, timestamp_get());
timestamp_add_now(TS_END_COPYRAM);
if (entry == (void *)-1)
die("failed to load ramstage\n");
}

32
src/mainboard/google/veyron_pinky/romstage.c
View file

@ -79,13 +79,8 @@ static void configure_l2ctlr(void)
void main(void)
{
void *entry;
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t start_romstage_time;
uint64_t before_dram_time;
uint64_t after_dram_time;
uint64_t base_time = timestamp_get();
start_romstage_time = timestamp_get();
#endif
timestamp_add_now(TS_START_ROMSTAGE);
console_init();
configure_l2ctlr();
@ -93,13 +88,10 @@ void main(void)
/* vdd_log 1200mv is enough for ddr run 666Mhz */
regulate_vdd_log(1200);
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = timestamp_get();
#endif
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_init(get_sdram_config());
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = timestamp_get();
#endif
timestamp_add_now(TS_AFTER_INITRAM);
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
mmu_config_range((uintptr_t)_dram/MiB,
@ -108,25 +100,19 @@ void main(void)
_dma_coherent_size/MiB, DCACHE_OFF);
cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
timestamp_add(TS_AFTER_INITRAM, after_dram_time);
#endif
entry = vboot2_load_ramstage();
if (entry == NULL) {
timestamp_add(TS_START_COPYRAM, timestamp_get());
timestamp_add_now(TS_START_COPYRAM);
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
CONFIG_CBFS_PREFIX "/ramstage");
timestamp_add(TS_END_COPYRAM, timestamp_get());
timestamp_add_now(TS_END_COPYRAM);
if (entry == (void *)-1)
die("failed to load ramstage\n");
}
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_add_now(TS_END_ROMSTAGE);
#endif
stage_exit(entry);
}

2
src/soc/rockchip/rk3288/Kconfig
View file

@ -32,6 +32,8 @@ config SOC_ROCKCHIP_RK3288
select ARCH_RAMSTAGE_ARM_V7
select HAVE_UART_MEMORY_MAPPED
select BOOTBLOCK_CONSOLE
select COLLECT_TIMESTAMPS
select HAS_PRECBMEM_TIMESTAMP_REGION
if SOC_ROCKCHIP_RK3288

3
src/soc/rockchip/rk3288/bootblock.c
View file

@ -26,11 +26,14 @@
#include <soc/grf.h>
#include <soc/timer.h>
#include <symbols.h>
#include <timestamp.h>
void bootblock_cpu_init(void)
{
rk3288_init_timer();
timestamp_early_init(timestamp_get());
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) {
switch (CONFIG_CONSOLE_SERIAL_UART_ADDRESS) {
case UART2_BASE:

3
src/soc/rockchip/rk3288/include/soc/memlayout.ld
View file

@ -39,7 +39,8 @@ SECTIONS
VBOOT2_WORK(0xFF708000, 16K)
OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K)
PRERAM_CBFS_CACHE(0xFF716000, 4K)
STACK(0xFF717000, 4K)
STACK(0xFF717000, 3K)
TIMESTAMP(0xFF717C00, 1K)
SRAM_END(0xFF718000)
/* 4K of special SRAM in PMU power domain. Careful: only supports 32-bit