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veyron: select rw romstage using vboot2

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this change makes veyron pinky to select a rw romstage using vboot2.

BUG=None
TEST=Booted Veyron Pinky. Verified firmware selection in the log.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

CQ-DEPEND=CL:219100
Change-Id: Ia1cfdacde9f8b17b00e7772a02e0d266afedb82f
Reviewed-on: https://chromium-review.googlesource.com/219103
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
This commit is contained in:
Daisuke Nojiri 2014-09-24 09:39:16 -07:00 • committed by chrome-internal-fetch
commit 69c1e4b9ee
9 changed files with 55 additions and 12 deletions
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1
configs/config.veyron_pinky
View file

@ -6,3 +6,4 @@ CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_ELOG=y
# CONFIG_CONSOLE_CBMEM=y
CONFIG_FLASHMAP_OFFSET=0x00100000
CONFIG_VBOOT2_VERIFY_FIRMWARE=y

5
src/mainboard/google/veyron_pinky/Kconfig
View file

@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOC_ROCKCHIP_RK3288
select MAINBOARD_DO_NATIVE_VGA_INIT
select HAVE_HARD_RESET
select RETURN_FROM_VERSTAGE
config MAINBOARD_DIR
string
@ -46,6 +47,10 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 0
config VBOOT_RAMSTAGE_INDEX
hex
default 0x3
config BOOT_MEDIA_SPI_BUS
hex
default 2

2
src/mainboard/google/veyron_pinky/Makefile.inc
View file

@ -16,8 +16,10 @@
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
bootblock-y += chromeos.c
bootblock-y += reset.c
verstage-y += chromeos.c
verstage-y += reset.c
romstage-y += romstage.c

5
src/mainboard/google/veyron_pinky/mainboard.c
View file

@ -57,13 +57,9 @@ static void setup_iomux(void)
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
/*i2c1 for tpm*/
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
/*i2c2 for codec*/
writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2);
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
@ -127,7 +123,6 @@ static void mainboard_init(device_t dev)
configure_sdmmc();
configure_emmc();
configure_i2s();
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
}
static void mainboard_enable(device_t dev)

14
src/mainboard/google/veyron_pinky/romstage.c
View file

@ -70,8 +70,6 @@ void main(void)
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
dcache_mmu_enable();
setup_chromeos_gpios();
cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
@ -79,7 +77,17 @@ void main(void)
timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
timestamp_add(TS_AFTER_INITRAM, after_dram_time);
#endif
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
entry = vboot_load_ramstage();
if (entry == NULL) {
timestamp_add(TS_START_COPYRAM, timestamp_get());
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
CONFIG_CBFS_PREFIX "/ramstage");
timestamp_add(TS_END_COPYRAM, timestamp_get());
if (entry == (void *)-1)
die("failed to load ramstage\n");
}
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_add_now(TS_END_ROMSTAGE);
#endif

21
src/soc/rockchip/rk3288/Kconfig
View file

@ -26,6 +26,7 @@ config SOC_ROCKCHIP_RK3288
select EARLY_CONSOLE
select DYNAMIC_CBMEM
select ARCH_BOOTBLOCK_ARM_V7
select ARCH_VERSTAGE_ARM_V7
select ARCH_ROMSTAGE_ARM_V7
select ARCH_RAMSTAGE_ARM_V7
select HAVE_UART_MEMORY_MAPPED
@ -49,9 +50,10 @@ config BOOTBLOCK_CPU_INIT
#
# 0xFF70_0000 TTB (16KB).
# 0xFF70_4004 Bootblock (max 16KB-4B).
# 0xFF70_8000 ROM stage (max 40KB).
# 0xFF70_8000 verstage then romstage (max 40KB).
# 0xFF71_2000 STACK (4KB).
# 0xFF71_3000 CBFS mapping cache (20K)
# 0xFF71_3000 CBFS mapping cache (4K)
# 0xFF71_4000 vboot work buffer (16K)
# 0xFF71_7FFF End of iRAM.
config SYS_SRAM_BASE
@ -74,6 +76,11 @@ config BOOTBLOCK_BASE
hex
default 0xff704004
# with vboot2, romstage is loaded over the verstage space
config VERSTAGE_BASE
hex
default 0xff708000
config ROMSTAGE_BASE
hex "ROM STAGE BASE"
default 0xff708000
@ -100,7 +107,15 @@ config CBFS_SRAM_CACHE_ADDRESS
config CBFS_SRAM_CACHE_SIZE
hex "size of CBFS cache data"
default 0x00005000
default 0x00001000
config VBOOT_WORK_BUFFER_ADDRESS
hex "memory address of vboot work buffer"
default 0xff714000
config VBOOT_WORK_BUFFER_SIZE
hex "size of vboot work buffer"
default 0x00004000
config CBFS_DRAM_CACHE_ADDRESS
hex "dram memory address to put CBFS cache data"

10
src/soc/rockchip/rk3288/Makefile.inc
View file

@ -29,6 +29,16 @@ bootblock-y += monotonic_timer.c
bootblock-y += clock.c
bootblock-y += spi.c
bootblock-y += media.c
bootblock-y += gpio.c
verstage-y += monotonic_timer.c
verstage-y += spi.c
verstage-y += timer.c
verstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
verstage-y += gpio.c
verstage-y += clock.c
verstage-y += i2c.c
verstage-y += media.c
romstage-y += cbmem.c
romstage-y += timer.c

7
src/soc/rockchip/rk3288/bootblock.c
View file

@ -25,14 +25,21 @@
#include "clock.h"
#include "grf.h"
#include "spi.h"
#include <vendorcode/google/chromeos/chromeos.h>
void bootblock_cpu_init(void)
{
writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
/*i2c1 for tpm*/
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
/* spi0 for chrome ec */
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rk3288_init_timer();
console_init();
rkclk_init();
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
setup_chromeos_gpios();
}

2
src/soc/rockchip/rk3288/media.c
View file

@ -24,7 +24,7 @@
int init_default_cbfs_media(struct cbfs_media *media)
{
#if defined(__BOOT_BLOCK__)
#if defined(__BOOT_BLOCK__) || defined(__VER_STAGE__)
return initialize_rockchip_spi_cbfs_media(media,
(void *)CONFIG_CBFS_SRAM_CACHE_ADDRESS,
CONFIG_CBFS_SRAM_CACHE_SIZE);