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Broadwell FSP: Successful execution of FspNotify

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Call FspNotify to finish the platform initialization.  Attempts to
load the payload.

BRANCH=none
BUG=None
TEST=Use the following steps to reproduce:
1.  Get the private FSP parts
2.  Copy configs/config.samus.fsp to configs/config.samus
3.  If running on a non-samus board, in
    src/mainboard/google/samus/Kconfig:
    a.  Comment out select EC_GOOGLE_CHROMEEC
    b.  Comment out select EC_SOFTWARE_SYNC
4.  If running on a non-samus board, in
    src/mainboard/google/samus/spd/spd.c comment out the check for
    valid SPD data at the end of the file
5.  Build and run on Samus
6.  Test successful if the code attempts to load the payload

Change-Id: I007bd5481e532e14dca3f158b8eb1d8cb4dc3f47
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/232874
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
This commit is contained in:
Lee Leahy 2014-12-01 15:54:31 -08:00 • committed by chrome-internal-fetch
commit ad87bce3bc
4 changed files with 23 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

3
configs/config.samus.fsp
View file

@ -3,6 +3,8 @@ CONFIG_USE_BLOBS=y
CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_GOOGLE_SAMUS=y
CONFIG_CBFS_SIZE=0x100000
CONFIG_HAVE_REFCODE_BLOB=y
CONFIG_REFCODE_BLOB_FILE="/build/samus/firmware/efi.elf"
CONFIG_CONSOLE_CBMEM=y
# Enable Serial Debugging
@ -37,6 +39,7 @@ CONFIG_FSP_RESERVED_MEM_SIZE=0x00400000
CONFIG_HAVE_FSP_BIN=y
CONFIG_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_PLATFORM_USES_FSP=y
CONFIG_HEAP_SIZE=0x00080000
# CONFIG_PCI_ROM_RUN is not set
# CONFIG_ON_DEVICE_ROM_RUN is not set

2
src/Kconfig
View file

@ -299,7 +299,7 @@ config TPM
If unsure, say N.
config HEAP_SIZE
hex
hex "Heap size in bytes"
default 0x4000
# Not used for the actual stack by ARM, but still needed in some src/lib/ files.

19
src/soc/intel/broadwell/chip.c
View file

@ -20,6 +20,9 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
#include <fsp_util.h>
#endif /* CONFIG_PLATFORM_USES_FSP */
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/intel/broadwell/chip.h>
@ -38,11 +41,27 @@ static struct device_operations pci_domain_ops = {
static void cpu_bus_noop(device_t dev) { }
static void broadwell_final(device_t dev)
{
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
/* Notify FSP done device setup */
printk(BIOS_DEBUG,
"Calling FspNotify(EnumInitPhaseAfterPciEnumeration)\n");
fsp_notify(EnumInitPhaseAfterPciEnumeration);
printk(BIOS_DEBUG, "Calling FspNotify(EnumInitPhaseReadyToBoot)\n");
fsp_notify(EnumInitPhaseReadyToBoot);
printk(BIOS_DEBUG, "FspNotify Returned\n");
#endif /* CONFIG_PLATFORM_USES_FSP */
}
static struct device_operations cpu_bus_ops = {
.read_resources = &cpu_bus_noop,
.set_resources = &cpu_bus_noop,
.enable_resources = &cpu_bus_noop,
.init = &broadwell_init_cpus,
.final = &broadwell_final,
};
static void broadwell_enable(device_t dev)

8
src/soc/intel/broadwell/romstage/romstage.c
View file

@ -225,14 +225,6 @@ void asmlinkage romstage_after_car(void)
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
#endif /* CONFIG_PLATFORM_USES_FSP */
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
/* TODO: Remove this code. Temporary code to hang after FSP TempRamInit API */
printk(BIOS_ERR, "Hanging in romstage_after_car!\n");
post_code(0x35);
while (1)
;
#endif /* CONFIG_PLATFORM_USES_FSP */
/* Run vboot verification if configured. */
vboot_verify_firmware(romstage_handoff_find_or_add());