The scope should be closed with `acpigen_write_scope_end`, rather
than `acpigen_pop_len`.
Change-Id: I80df2ee1b51d7dbba85e556bee0fd7513ac933bb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86500
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some upcoming patches run up against the existing limit, which
was added 16 years ago without any justification as to the size.
Bump the size from 10 to 15, to prevent tripping the runtime assertion.
TEST=Tested with rest of patch train
Change-Id: I8362b3a63a23bea0ce47920e5d41cd2535dbc084
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit adds support for VMD (Volume Management Device) in the
Panther Lake SoC. VMD is a feature that allows the management of NVMe
storage devices by abstracting the PCIe root complex. It provides a way
to manage multiple NVMe drives more efficiently.
Changes include:
- Adding VMD to the `min_pci_sleep_states` array in `acpi.c`.
- Updating `chipset.cb` to include the VMD device.
- Disabling the VMD device by default.
- Introducing a new function `fill_fsps_vmd_params`.
- Defining the VMD device and function numbers in `pci_devs.h`.
BUG=b:391083063
TEST=Able to build and boot google/fatcat. Observed that VmdEnable UPD
is disabled in debug FSP logs.
Change-Id: Ie391196e7b4537d1146ac30177a0ba472a1bfb43
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Update header files for FSP for Panther Lake platform to version
3015_00, with the previous version being 2454_00.
Changes include:
- Updating UPD Offset in FspmUpd.h and FspsUpd.h
- Adding Sign-of-Life related UPDs in FspmUpd.h
- Adding VMD related UPDs in FspsUpd.h
BUG=b:394189627
TEST=Able to build google/fatcat.
Change-Id: I87176515d4bdd8906842fd7c2ade1e6acd339212
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86297
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The Fn key on kanix emits the scancode 94 (0x5e).
BUG=b:384580437
TEST=Build and test on kanix, the fn key works normally
Change-Id: Ia693813dafe1bd35840dfb892827598a7ca9c88f
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85438
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In the Panther Lake architecture, each GPIO community functions as a
separate pin control entity. Therefore, when specifying a GPIO
identifier, one should use the community-specific offset, not the number
from the first pad within the GPIO series. This is achieved by selecting
the Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES within
the Panther Lake SOC Kconfig file.
The numbers within the _CRS GpioInt and GpIo objects in the SSDT should
be offsets within the community. The GPIO identifier employed should
correspond to the offset from the respective community.
Let's take an example. In the fatcat board overridetree.cb,
ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) points to GPIO Group E. The pad
starts at 74. It is inside community 1, which starts at 48. The correct
GPIO reference is (19 + 74) - 48 = 45, or 0x002D in hexadecimal.
Here are two notable changes in the fatcat board SSDT introduced by this
commit.
- ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)
"\\_SB.PCI0.GPI1", 0x00, ResourceConsumer, ,
)
{ // Pin list
- 0x0033
+ 0x002D
}
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
- ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)
"\\_SB.PCI0.GPI3", 0x00, ResourceConsumer, ,
)
{ // Pin list
- 0x0050
+ 0x003B
}
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
This change is verified via S0ix in Google Fatcat board with
touchscreen/touchpad attached as the wake source.
BUG=none
TEST=Check the number from CRS GpinInt and GpIo objects in the SSDT, and
ensure that the GPIO number used matches the community offset.
Configure touchscreen/touchpad in THC-i2c mode on factcat board and
enter S0ix and check that it can be waked by touchscreen/touchpad.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit enables Thunderbolt authentication for Panther Lake by
assigning `ioe_tcss_valid_tbt_auth` to the valid_tbt_auth field in
`soc_tcss_ops`.
For the SoC's integrated PD solution, AUX BIAS PAD programming is not
required and has been removed.
TEST=Verified all USB-C ports are functional.
With this patch, \_SB.PCI0.TDM0._DSD exists in the SSDT, containing:
```
Scope (\_SB.PCI0.TDM0)
{
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("c44d002f-69f9-4e7d-a904-a7baabdf43f7"),
Package (0x01)
{
Package (0x02)
{
"IMR_VALID",
One
}
},
ToUUID ("6c501103-c189-4296-ba72-9bf5a26ebe5d"),
Package (0x01)
{
Package (0x02)
{
"WAKE_SUPPORTED",
One
}
}
}
```
Change-Id: I28eac7cfd6511d8680cdae4f830afa73ad201a17
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Updating from commit id 15e5c6c91d48:
2024-12-05 16:00:37 +0100 - (Merge changes I00d2de7b,I5ec82646 into integration)
to commit id 0c370e2d592b:
2025-02-04 18:14:07 +0100 - (Merge "feat(mt8196): add SMMU driver for PM" into integration)
This brings in 414 new commits.
Change-Id: I5cb4fab45fb82463f0ae3332e46995d30d123352
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86478
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are unnecessary because they are the same as the chipset
devicetree defaults.
Change-Id: Id26f09674457720ad56a19b6b0884b8012be9019
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86412
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch prevents exposing the CPU JTAG GPIO pads. These are
internal GPIO pins used for debugging the SoC and should not be
configurable from the kernel pinctrl driver.
TEST=Able to build and boot google/fatat. Decompile ACPI table
using iasl and ensure CPUJTAG entry not present.
Change-Id: I4d920acb95275fbf72b83b822eddc41829511626
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Dirks is a Chromebox device, so select SYSTEM_TYPE_BOX for it. Other
nissa variants will continue to have SYSTEM_TYPE_LAPTOP selected.
BUG=b:389391653
TEST=emerge-nissa coreboot
check CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
check CONFIG_CR50_RESET_CLEAR_EC_AP_IDLE_FLAG=y
Change-Id: Iabc9afdfdb07d4d6cb4d3fb4b43bfdc3cf2aa383
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Add config SYSTEM_TYPE_BOX to allow proper system type selection for
devices like chromebox, mac-mini etc.
Change-Id: I887413cbc09fb0725b2ffd621fe10991b7dbcf6d
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86396
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
It will cause suspend to fail to enter S0ix. After discussion
with SOC and HW teams, remove GPP_B5 and B6 as ISH function and
disable ISH on the devicetree.
BUG=b:383696667, b:395005219
TEST=emerge-nissa coreboot
Change-Id: Id3d26f1b604b889f4fdb6e45218f4118499c303e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Ife30f73495d44c98717e147602de10f5a6a89358
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Ic226fd93b431467c7fa3a53140102ff4fd327f40
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86271
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Id28a29481f9a1bc570e47a9cb75613d3621b0d44
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86270
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables the `HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR`
Kconfig option for Alder Lake SoC platform that has support for
CHROMEOS_ENABLE_ESOL.
This allows the eSOL feature (depending upon CHROMEOS_ENABLE_ESOL)
to display a low-battery indicator.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: I8b49a487ca80a2aeeb8b4d8e4c2259217e854444
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86316
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit implements early handling of critical low battery
conditions in the romstage for Alder Lake platforms.
A message is displayed to the user via
ux_inform_user_of_poweroff_operation. A short delay is introduced to
allow the user to see the message. A low battery event is logged.
The system is shut down via the Chrome EC.
This early handling prevents the system from proceeding with
boot (while performing firmware update) if the battery is critically
low and ensures a clean shutdown. This is particularly important for
ChromeOS devices.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: Ib4be86ed17818ee05b7bec0337a90f80017183c2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86227
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit implements `platform_is_low_battery_shutdown_needed` and
callback for ChromeOS.
- platform_is_low_battery_shutdown_needed: API to check if low battery
shutdown is needed.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: I119f80a45c045a6095cae98f179c755a2e948e9c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit adds the `platform_is_low_battery_shutdown_needed` callback
to the FSP API. This allows platforms to integrate low-battery handling
logic directly into the FSP silicon initialization process. By checking
for critical conditions (e.g., low battery) within this callback after
FSP silicon initialization, the platform can initiate a controlled
shutdown before proceeding with further boot stages, preventing abrupt
shutdowns later in the boot process.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I2d6677d70dea3d24f5a19d70608fd21229a271a0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86226
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit adds a `do_low_battery_poweroff()` function to handle
platform power off due to critically low battery levels.
This provides a standardized way to handle low battery shutdowns across
platforms.
Additionally, the delay to the `do_low_battery_poweroff()` function,
allowing time for the low battery indicator to be displayed before
powering off. The delay is configurable through the
`PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC` Kconfig option.
Finally, a low battery indicator event is logged using `elog`
before the delay.
This functionality (elog and delay) is enabled when the
`PLATFORM_HAS_LOW_BATTERY_INDICATOR` Kconfig option is selected.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I92e9003c70c2608770972f1a302f954ebdf17bc4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86361
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds low battery indicator bitmap into CBFS. This screen
is displayed when the system detects a critically low battery condition.
The screen displays a logo and can be configured with a custom path.
An option to display an early low battery indicator in text mode is also
included. This early indicator can defer the firmware update.
This feature is controlled by the PLATFORM_HAS_LOW_BATTERY_INDICATOR
Kconfig option.
BUG=b:339673254
TEST=Able to see low-battery user notification in text mode before
memory init. Verified low-battery boot event listed in the eventlog.
Change-Id: I711c53455639b449fe85903139bbc06cdab08d09
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit refactors the logo.bmp inclusion logic to use a helper
macro, `add_bmp_logo_file_to_cbfs`. This centralizes the logic for
adding BMP logo files to the CBFS image and improves code readability.
Change-Id: I135c1f2af02064b72bc1f747336ac98ffdb20842
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86368
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit moves the logo.bmp inclusion logic from
`src/drivers/intel/fsp2_0/Makefile.mk` to `src/lib/Makefile.mk`.
This change centralizes the logo inclusion logic within the `lib`
directory, aligning it with the location of `bmp_logo.c` and making
it independent of the FSP 2.0 driver.
Change-Id: I16ed1cf29b839c25b6ea1c2f10faf3d99dd707c9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit renames the `google_chromeec_do_early_poweroff()` function
to `platform_do_early_poweroff()`, aligning it with the API that adds
early power off support using the Chrome EC.
It selects the `HAVE_EARLY_POWEROFF_SUPPORT` Kconfig option for platform
to perform early power off procedures.
Change-Id: I0c634d69de36fe8bdb6a61c121e321d3626ac3ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit adds support for early power off on Intel platforms
along with existing PMC based implementation to support power off
at later stage (like ramstage).
A new function, `platform_do_early_poweroff`, is added to the
pmclib to handle platform-specific early power off procedures.
This function is called before memory initialization (in romstage or
earlier).
Note: While Intel chipsets do not support power off before silicon
initialization, this change leverages Chrome EC APIs to enable power off
in romstage for low-battery boot on ChromeOS devices. Power off failures
in ramstage prior to FSP-S are outside the scope of this change.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit introduces the `HAVE_EARLY_POWEROFF_SUPPORT` Kconfig option
and the `platform_do_early_poweroff()` API.
The Kconfig option enables platform-specific early power off support,
which is often required on Intel platforms. The corresponding API allows
platforms to implement the necessary hardware operations for early power
off, typically before memory initialization.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I05b9882e100825a4fb733163a65f820c8c943361
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86417
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a function ux_inform_user_of_poweroff_operation
to display a message on the screen when the system is powering off due
to critically low battery. The message is centered on the screen and
displays a localized string "Battery critically low. Shutting down.".
If no localized string is found, a default English message is displayed.
This implementation relies on CHROMEOS_ENABLE_ESOL Kconfig which is used
to render text message for early sign-of-life.
BUG=b:339673254
TEST=Able to capture the eventlog for low battery boot event.
Change-Id: I3b24d2c89ade8cc62b7e47c487d52d47b7f3376d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86224
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a new UX locale message to display a warning when the
battery is critically low.
The message informs the user about the low battery and indicates that
the system is shutting down.
This change ensures that users are notified before the system
unexpectedly shuts down due to low battery.
BUG=b:339673254
TEST=Built and booted google/brox.
Change-Id: I75c7a0d4d439901098c7f17a1dc90355307116ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit introduces `ux_inform_user_of_operation` to reduce code
duplication when displaying UX messages.
`ux_inform_user_of_update_operation` now calls this helper, passing
the message ID. This allows easier addition of other UX messages.
BUG=b:339673254
TEST=Built and booted google/brox. Verified display eSOL.
Change-Id: Ib31f7633e7b3f84122419e4ce39e2b5044cb9a96
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86278
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch refactors the `ux_locales_get_text` API to handle fallback
text (English) internally, rather than relying on the caller. It
introduces message IDs for lookups, enabling the API to locate both
the UX locale name and fallback text based on the ID.
With this patch, `ux_locales_get_text` API locates UX locales message
based on message ID.
`ux_locales_get_text` retrieves fallback text message depending
upon the message ID if UX locales is not available.
This centralizes fallback handling and simplifies adding future
messages without per-SoC duplication.
BUG=b:339673254
TEST=Built and booted google/brox. Verified eSOL display.
Change-Id: I4952802396265b9ee8d164d6e43a7f2b3599d6c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Increase PL4 power limit values for all Intel PTL-H variants on Fatcat
from 50000 to 65000 to ensure successful boot and adequate performance
with 45W and 65W USB-C adapters. This prevents system bottlenecks when
using lower-wattage power supplies.
BUG=b:395130929
TEST=Verified successful boot with 45W and 65W USB-C travel adapters,
as well as 96W/106W USB-C adapters.
Change-Id: I6073e748e9f8c7317f0ad9a1193699e34703bdba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86388
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Spike Simulator commit 191634d2854d implemented a ns16550 serial device
which puts the base address at 0x10000000.
Tested: Start Spike Simulator and see that coreboot prints onto the UART.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0e3db9d8b141c733bf609f906018096e3594ce83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85852
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Dirks are chromebox, so they need different settings in ec.h.
Add a new dirks baseboard ec.h and use it for dirks.Remove
everything related to:
- Lid
- Battery
- Built-in keyboard
- AC connect/disconnect
- Mode changes
BUG=b:389391653
TEST=emerge-nissa coreboot
Change-Id: I8089a2aff3032a4271212765f65881a09f42c1ae
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86354
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Only print the warning if Linuxboot payload is actually selected,
because we don't care otherwise.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I5008d685c52c1d4e0d7eba44c964c51a2a6f99c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85957
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add the tooling necessary to build an Image that can be found and
started by ROM code of the JH7110 SOC.
source: https://github.com/starfive-tech/Tools
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iab16c1e1f15f24e85c0ef1a3e838d024e1e49286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83849
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently all platforms on RISC-V require a FDT.
The inclusion of the FDT is currently done in the platform Makefiles.
In order to factor out some common code this patch adds the inclusion
in the architecture Makefile. The FDT must be aligned to 8 byte
according to device tree spec. It avoids misaligned access.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I3b304a89646fe84c98e9f199f315bebb156de16c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* Move x86_64 documentation to dedicated page
* Update with better description of current implementation
* Update TODOs
Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Local tags (e.g. to keep track of builds) should not be used to describe
a board status report. This has happened in some cases, e.g. [1].
According to the Git 2.41.0 manual for git-describe, the '--tagged'
parameter is a way to also use any "lightweight (non-annotated) tag" in
addition to annotated tags, which are always used even without this
parameter. All coreboot release tags seem to be annotated, so this
option should be safe to drop.
[1] https://review.coreboot.org/plugins/gitiles/board-status/+/b8c47429bad5afc5cd7f798cad3dece9790a1f83
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I54b302415e569a3385559cc85323ce34462042ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79837
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The QEMU Bochs display driver uses 0x1CF as its VBE DISPI data port, but
this is only present on x86. Instead, use the port at 0x1D0 [1] which is
available on both x86 and non-x86 architectures. The data port is also
calculated inline based on the VBE DISPI index port while reading and
writing, update those expressions as well.
[1] https://web.archive.org/web/20240404032816/https://www.qemu.org/docs/master/specs/standard-vga.html#io-ports-used
Change-Id: I899beb742d42c26f3e57023f05ff459094fce5f1
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82061
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Craask cannot boot into OS from 2nd source eMMC.
Update eMMC DLL tuning value to improve initialization reliability
BUG=b:375497774
TEST=Cold reboot stress test over 2500 cycles
Change-Id: I415beb84ac09f8c3e80c3df12bc323a06baf812d
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86395
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the EVT's circuit(kanix_250116.pdf) change,
update LAN clock request to GPP_C11.
BUG=b:386025819
BRANCH=firmware-rex-15709.B
TEST=emerge-rex coreboot chromeos-bootimage; test LAN function on kanix
Change-Id: I5d27585717897203d6ac81ca47551be5771918c3
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86397
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
