mb/trulo/var/uldrenite: Remove GPP_B5 and B6 as ISH function

It will cause suspend to fail to enter S0ix. After discussion
with SOC and HW teams, remove GPP_B5 and B6 as ISH function and
disable ISH on the devicetree.

BUG=b:383696667, b:395005219
TEST=emerge-nissa coreboot

Change-Id: Id3d26f1b604b889f4fdb6e45218f4118499c303e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
John Su 2025-02-14 16:08:01 +08:00 committed by Matt DeVillier
commit 19bcc7653b
2 changed files with 5 additions and 4 deletions

View file

@ -61,10 +61,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PWROK, LEVEL, INVERT),
/* B4 : PROC_GP3 ==> EN_PP3300_UCAM_X */
PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
/* B5 : GPP_B5 ==> ISH_I2C0_SCL */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
/* B6 : GPP_B6 ==> ISH_I2C0_SDA */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
/* B5 : GPP_B5 ==> NC */
PAD_NC(GPP_B5, NONE),
/* B6 : GPP_B6 ==> NC */
PAD_NC(GPP_B6, NONE),
/* B7 : GPP_B7 ==> NC */
PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
/* B8 : GPP_B8 ==> NC */

View file

@ -490,6 +490,7 @@ chip soc/intel/alderlake
end
probe DB_CELLULAR CELLULAR_RW350R
end # PCIE2 WWAN card
device ref ish off end
device ref shared_sram on end
device ref heci1 on end
device ref pmc hidden end