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mb/google/fatcat/var/francka: Configure the finger print pins

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Configure correct finger print pins, And change power sequence.
FP_PWR_EN - GPP_H03
FP_RST_OD - GPP_H17
FPMCU_INT - GPP_D17
FPMCU_FW_UPDATE - GPP_F20

BUG=b:393985006
TEST=Boot to OS in francka and fingerprint function work well.

Change-Id: I0d9b1d042da1bd81d0f3a32140247948cdab983c
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Ian Feng 2025-02-14 13:54:57 +08:00 • committed by Matt DeVillier
commit 5688932d25
2 changed files with 20 additions and 14 deletions
Download patch file Download diff file Expand all files Collapse all files

20
src/mainboard/google/fatcat/variants/francka/gpio.c
View file

@ -186,7 +186,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_D16: HDA_RST# */
PAD_NC(GPP_D16, NONE),
/* GPP_D17: FPMCU_INT# */
PAD_CFG_GPI_INT(GPP_D17, NONE, PLTRST, LEVEL),
PAD_CFG_GPI_IRQ_WAKE(GPP_D17, NONE, PWROK, LEVEL, INVERT),
/* GPP_D18: CLKREQ_PCIE#6 */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
/* GPP_D19: SOC_SD_RST# */
@ -286,16 +286,16 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_F14, NONE),
/* GPP_F15: Not used */
PAD_NC(GPP_F15, NONE),
/* GPP_F16: SOC_THC_1_RST# */
PAD_CFG_GPO(GPP_F16, 0, DEEP),
/* GPP_F16: Not used */
PAD_NC(GPP_F16, NONE),
/* GPP_F17: SOC_THC_1_CS# */
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5),
/* GPP_F18: SOC_THC_1_INT# */
PAD_CFG_GPI_APIC(GPP_F18, NONE, PWROK, LEVEL, INVERT),
/* GPP_F18: Not used */
PAD_NC(GPP_F18, NONE),
/* GPP_F19: Not used */
PAD_NC(GPP_F19, NONE),
/* GPP_F20: AP_FP_FW_UP_STRAP */
PAD_CFG_GPO(GPP_F20, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_F20, 0, LOCK_CONFIG),
/* GPP_F22: Not used */
PAD_NC(GPP_F22, NONE),
/* GPP_F23: SLP_S0#_GATE */
@ -308,7 +308,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_H02: Not used */
PAD_NC(GPP_H02, NONE),
/* GPP_H03: EN_PWR_FP */
PAD_CFG_GPO(GPP_H03, 0, DEEP),
PAD_CFG_GPO(GPP_H03, 1, DEEP),
/* GPP_H04: COEX1 */
PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2),
/* GPP_H05: COEX2 */
@ -334,7 +334,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_H16: SOC_AUDIO_STRAP */
PAD_CFG_GPI(GPP_H16, NONE, DEEP),
/* GPP_H17: FP_RST_1V8_OD# */
PAD_CFG_GPO(GPP_H17, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_H17, 1, LOCK_CONFIG),
/* GPP_H19: Not used*/
PAD_NC(GPP_H19, NONE),
/* GPP_H20: Not used */
@ -420,10 +420,10 @@ static const struct pad_config romstage_gpio_table[] = {
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
/* GPP_C01: SOC_SMBDATA */
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
/* GPP_F16: SOC_THC_1_RST# */
PAD_CFG_GPO(GPP_F16, 0, DEEP),
/* GPP_H03: EN_PWR_FP */
PAD_CFG_GPO(GPP_H03, 0, DEEP),
/* GPP_H17: FP_RST_1V8_OD# */
PAD_CFG_GPO(GPP_H17, 0, DEEP),
};
const struct pad_config *variant_gpio_table(size_t *num)

14
src/mainboard/google/fatcat/variants/francka/overridetree.cb
View file

@ -62,6 +62,12 @@ chip soc/intel/pantherlake
[PchSerialIoIndexI2C4] = PchSerialIoPci,
}"
register "serial_io_gspi_mode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
}"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@ -292,13 +298,13 @@ chip soc/intel/pantherlake
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)"
register "wake" = "GPE0_DW2_15"
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D17_IRQ)"
register "wake" = "GPE0_DW1_17"
register "has_power_resource" = "true"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H03)"
register "enable_delay_ms" = "3"
device spi 0 hidden end
device spi 0 on end
end # FPMCU
end
end