The mipi_cmd_func_t callback for mipi_panel_parse_init_commands()
currently doesn't support passing additional data for storing context.
Therefore user code would need to store any extra data in global
variables. For example, in the upcoming DSI dual channel support for
MediaTek platforms, the callback needs to know whether the MIPI panel
supports dual channel or not. To support that use case, pass an extra
`user_data` argument to mipi_cmd_func_t.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: Id5d7b168cdcadfe8d8435c29d7e855a535815057
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Refactor the stack definition macros to explicitly define separate
memory regions for the stack, addressing resource conflicts on
certain SoCs like Qualcomm x1p42100.
The original STACK macro is split into PRERAM_STACK and
POSTRAM_STACK.
Motivation:
On the Qualcomm x1p42100 SoC, the boot flow presents two
constraints for the initial stack location:
- Boot IMEM is unavailable after the ADSP is loaded.
- The existing SSRAM stack address is reserved for QC QSEE by the
Trust Zone.
Solution:
- PRERAM_STACK: Used by coreboot (e.g., till romstage) for static
stack allocation (from an alternative SSRAM or BOOT IMEM region).
- POSTRAM_STACK: Used starting from ramstage, leveraging the
DRAM-mapped memory.
This conditional split allows coreboot to manage stack memory
independently for the limited environment before DRAM is fully
initialized (ENV_ROMSTAGE_OR_BEFORE), resolving the hardware memory
conflicts while maintaining compatibility with existing code via
aliasing.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
Change-Id: I6356adc63d595f59050e6dc5961404be4a9534c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90402
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
The Armv9-A architecture introduces the Memory Tagging Extension (MTE),
which uses a dedicated memory region for tag storage.
This patch adds a new memory type, BM_MEM_TAG, to allow for the proper
accounting and reservation of this memory region. This ensures that the
payload, e.g. depthcharge, can correctly identify and utilize the tag
storage area.
BUG=b:438666196
Change-Id: I2f6d2b3c2c1a8e1f0e9b2c3d4e5f6a7b8c9d0e1f
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch introduces a new function, bootmem_add_range_from, which
allows adding a memory range of a specific type only if it is carved
out from a range of another specific type. This is useful for cases
where memory needs to be allocated from a pre-defined region.
The function checks if the target range is fully contained within a
range of `from_tag` before marking it as `new_tag`. Error reporting
is included to log cases where the allocation is not possible.
BUG=b:438666196
Change-Id: Icfdb5ef9114572c075be6ef4e57d00151300a17a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90469
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GCC generates correct code for __builtin_bswapXX() on all architectures,
including ArmV4. It seems that whatever bug caused this to not work back
in commit 879ea7fce8 ("endian: Replace explicit byte swapping with
compiler builtin") has been fixed now. We can eliminate the swabXX()
functions and simplify the code.
All instances that had been calling these functions directly should have
been using real endianness conversions anyway.
Change-Id: I19713fd009aa5c0e01c4a42e0cf012364d6bed60
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90438
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
We've accumulated a number of endianness-handling and related macros
that are duplicated between coreboot and libpayload. This patch reduces
duplication by merging them into a commonlib header. This has the added
side-benefit of bringing the coreboot implementation of beXXenc/dec()
functions to libpayload, which lead to better code generation by
avoiding https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716.
Keep the htobell()-style functions in libpayload only since they're not
needed in coreboot and not preferred. Keep the cpu_to_beXX()-style
functions in coreboot only -- maybe we should deprecate those
eventually.
This patch is explicitly copying and relicensing some of the code I
originally added as GPLv2 in commit e8e92d60c4 ("endian.h: Add
be32dec/be32enc family of functions") to BSD-3.
Change-Id: I5eb83d44a98b3aa59bba65b8e22df668874d2668
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90308
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The option was introduced by
commit ae738acdc5 ("cpu/x86: Support CPUs without rdmsr/wrmsr")
for the intel quark SOC. However the SOC doesn't exist anymore in
coreboot. Nor does any other SOC use this option.
Therefore remove it.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4f3f5e91c00784c159042271387c2e862f351881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90421
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Parse the supported voltages from the DDR3 SPD and populate the
corresponding fields in CBMEM_ID_MEMINFO to make sure the SMBIOS
type 17 tables report the actual supported voltages of the DIMM.
Change-Id: I35af7c23f285af10b607a80eab7f4d9df664b3fd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
If the Top Swap mechanism is enabled, after running the bootblock from
the TOP_SWAP region, boot from an updatable COREBOOT_TS FMAP region.
Having flashed the TOP_SWAP bootblock and COREBOOT_TS, this allows the
user to boot a newer version of the firmware with the ability to
revert to the previous known-good version by performing a CMOS reset.
Requires having a read-write COREBOOT_TS region in the FMAP file.
This is part of an ongoing implementation of a redundancy feature
proposed on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
TEST=Boot Protectli VP6650, setting the attempt_slot_b flag to
different values, observing the "Booting from COREBOOT/COREBOOT_TS
region" prints correspondingly.
Change-Id: Ieadc9bfbe940cbec79eb84f16a5d622bfbb82ede
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Verstage cannot use the UEFI variable store because it runs before
the SMMSTORE is initialized/available, and because the required EDK2
headers are x86-specific. Provide inline stub that returns fallback
values to satisfy console_init() dependency.
TEST=build google/dewatt with CFR enabled
Change-Id: Icaa493692006cf3e0bb194ee3fdd9caf2f51cda1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch adds the Display Stream Compression (DSC) related structures
to the panel header. These structures define the rate control parameters
and configuration options required by the DSC engine for frame
compression, such as quantization parameter ranges, bits per group
offset, compression enable flag, dual DSC support, and line buffer
depth.
BUG=b:424782827
TEST=Build pass, boot ok, display ok
Change-Id: Icec24f55b962cd2794a79a68fc8fecec43300103
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90129
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves all the definitions and declarations that are part of the
ACPI Platform Error Interface (APEI) into the corresponding header file.
Change-Id: Ied3915e4f598cd393f396de26b07ade7ce3a7ab1
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This commit adds the relevant DIDs to support Tiger Lake H (TGL-H) systems based on the Xeon W-11865MRE (GPU) and RM590E chipset (PCH).
TEST=A platform with Xeon W-11865MRE and RM590E booted
the relevant information printed in coreboot log.
[DEBUG] CPU: ID 806d1, Tigerlake R0, ucode: 00000056
[DEBUG] MCH: device id 9a36 (rev 05) is Tigerlake-H-8-1
[DEBUG] PCH: device id 4390 (rev 11) is Tigerlake-H RM590E
[DEBUG] IGD: device id 9a70 (rev 01) is Tigerlake H GT1 32EU
Change-Id: I2bff2551b9f194e169c0edd080e9c869bcc9c60f
Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90179
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Chromium OS EC has some specialized handling of chromebook specific
function keys on the keyboard top row, these have a function specific
action key code that is exposed to the OS and used to map their
position, and also a specific scancode that has to be mapped to a Linux
event code.
This adds the necessary mapping for KEY_HOMEPAGE, which is going to be
used in new devices.
The scancode picked is 0xe012, which maps to e02a or 0xaa, the
corresponding EC CL is:
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/7118961
BUG=b:446007724
TEST=flashed and tested on a brox board with chromiumos, checked the
code with evtest
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I395721a342f507453dae19373df2f189ac1b5dac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90024
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
memory_info with dimm_info entries is available as CBMEM_ID_MEMINFO.
Moving the structures definitions to the commonlib allows the payloads
to easily access the memory information.
BUG=b:450374306
TEST=Build and boot Google/Brya
Change-Id: I25e788d5afd668e93f8ea60adaefb7b8b5d5ec28
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Refactor the DMA coherent memory region definition to support
stage-specific allocations.
In some boot flows, it is necessary to define separate DMA coherent
buffers for the early boot stage (e.g., romstage/bootblock) and the
later stage (ramstage). It allows the firmware to use only the memory
it needs, where it needs it, and prevents small-scale memory constraints
from crippling the overall boot flow.
The arch-specific, and now redundant, definitions of DMA_COHERENT are
removed from arm/memlayout.h and arm64/memlayout.h.
BUG=b:456953373
TEST=Able to build google/quenbi.
Change-Id: Ic32d14dda6cda0f731233dd3d86f3215c6af3637
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90049
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extend the lb_framebuffer_flags struct to include one more bitfield
'has_dual_pipe' to indicate dual pipe support.
TEST=firmware display ok, in depthcharge with https://crrev.com/c/7129839
BRANCH=none
BUG=b:424782827
Change-Id: I082be80b4606090ed219820a407d80d9f429ea7e
Signed-off-by: Nancy Lin <nancy.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90038
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Include guards should cover the whole file.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Idbb7b26b31460ad5ac6b8a55a41eb274a8fcec92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Add a new member 'flags' to the panel structure in panel.h, and define
`PANEL_FLAG_CPHY` to indicate C-PHY interface support. This change
enables panel drivers to check and handle C-PHY panels.
BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=build passed
Signed-off-by: Bincai Liu bincai.liu@mediatek.corp-partner.google.com
Signed-off-by: Vince Liu vince-wl.liu@mediatek.corp-partner.google.com
Change-Id: I4c35ad2cb6fc2289598ae47b3abf1c6c706dad42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89760
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
note: The entire patch was created using AI (besides commit-msg)
Change-Id: I0f80d1d8cd67b26a4ec1014584b5486254115839
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Co-authored-by: aider (openrouter/anthropic/claude-sonnet-4) <aider@aider.chat>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89677
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To save memory, only allocate and configure the framebuffer when display
output is required during boot.
This is achieved by:
1. Making the `framebuffer` memory region optional.
2. Guarding the framebuffer's uncached MMU configuration with a
`display_init_required()` check.
This ensures the framebuffer is prepared only when needed, saving
memory on boot paths that do not require display.
BUG=b:319511268
BRANCH=none
TEST=emerge-rauru coreboot
Change-Id: I3808031160e421de7c21f585f4b79d42bfddccc4
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89541
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit makes the tile and die ID CPU topology parameters
information available to support the implementation of
EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo() in accordance with the
Platform Initialization Specification 1.7.
TEST=Instrumentation shows that the tile_id and die_id apic_path fields
are properly populated.
Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d64
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89461
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refactors the handling of CPU IDs for the Pantherlake and
Wildcat Lake series by using a single CPU ID mask instead of listing
each individual stepping. This change simplifies the code by reducing
redundancy and making it easier to manage CPU IDs.
Previously, each stepping of the Pantherlake series had its own entry,
which led to unnecessary complexity. By consolidating these into a
single entry with a mask, we improve maintainability and reduce
potential errors.
These modifications do not affect the existing functionality but
streamline the codebase for future updates and maintenance.
TEST=CPU ID c06c1 is properly identified as "Pantherlake".
Change-Id: Ie52ed860c096a3d157ae6580aeedf3acb8c723ab
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89375
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add enums for the output pin widget node IDs for Realtek ALC887 [1] and
use these enums in the motherboard configuration.
[1] Figure 1, Block Diagram, ALC887-GR Datasheet, Rev. 1.0, 24 July 2008
Change-Id: Iaa2ebd7447a19dfc98b006c851f1605851c1ea5d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This moves most of the vendor and architecture independent code into
common ACPI code.
Change-Id: I7dca939612a5f3d8d6a148fa67bf0ce891952584
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88034
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current implementation of the HDA verb table has been shown to have
some problems. The primary issue is that it requires the programmer to
keep track of the amount of verbs that are going to be loaded. While
this may sound simple, in practice there have been numerous cases where
this "count field" has been forgotten to be updated or miscounted. In
the case where the "count field" is incorrect, coreboot will start
looking for codecs in some random memory location, essentially making
loading further codecs impossible.
Another issue is the "count field" treats 4 32-bit values as a single
group, therefore the amount of verbs in the table must be a multiple
of 4. This makes intuitive sense when only using the AZALIA_PIN_CFG() or
AZALIA_SUBVENDOR() macros. However, once the verb table requires
"controls" that use < 4 verbs (e.g. "Coefficient Index"), we need to add
padding values to ensure the alignment is correct. This adds unnecessary
verbs to the table which can further lead to unnecessary processing.
Therefore, in this change we proprose a solution by separating the codec
entries in the verb table into structures, which allows us to separate
the verbs into an array and automatically calculate the "count field"
using the ARRAY_SIZE() macro. It also makes iteration and access to
member fields easier. We also now count the verbs and not 4 32-bit
groups, eliminating the aforementioned alignment issue.
Additionally, this change also changes the way coreboot searches for
entries in the verb table. Before, we searched the table for only a
matching vendor ID, but now we search for a matching vendor ID and
codec address pair. This allows a mainboard to be able to correctly load
multiple audio codecs that use the same chips.
To make reviewing this large rework easier, we temporarily keep both
implementations (legacy and reworked) and allow boards to choose which
implementation to use by selecting a Kconfig. Newer boards are
discouraged from using the legacy implementation, as it is not selected
by default. This allows us to slowly change the codebase instead of
changing everything at once.
TEST=
1. Timeless build with AZALIA_USE_LEGACY_VERB_TABLE=y produces
identical binaries (with INCLUDE_CONFIG_FILE=n)
2. HP ProBook 450 G3 using reworked verb table was able to load all
verbs successfully.
Change-Id: Ib16237de89956405afa3be5b4e3f64a4d62e6a48
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88656
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a new library, `vga_gfx`, to handle text
rendering on a VGA planar buffer. The new functionality supports
displaying text with various screen orientations (Normal, Left Up,
Bottom Up, and Right Up).
The key features are:
- A new public API, `render_text_to_bitmap_buffer()`, that takes a
text string, screen orientation, and buffer as input.
- Automatic text wrapping to fit the screen's effective width,
considering the specified orientation.
- The `vga_gfx.c` library is conditionally compiled for both
`romstage` and `ramstage` based on `CONFIG_VGA` and
`CONFIG_ROMSTAGE_VGA` respectively.
- Text is rendered as a 1-bit-per-pixel bitmap and then cropped
to its bounding box to optimize the output size.
- The `bootsplash.h` header file is updated with the new API
prototype and related constants.
This implementation allows for flexible text display, which is
crucial for showing user notifications on devices that may
operate in a rotated display mode.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: I80fcf0a3f106a44f8e4ecdeec38f54ff09f86e6f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add support for Class-D Smart Amplifiers: CS35L56, CS35L57 and CS35L63.
CS35L56 and CS35L57 are 18.5 V Class D Smart Amplifiers with Multi-Cell
Battery Boost.
CS35L63 is a PC Smart Amplifier with Speaker Protection and Audio
Enhancement Algorithms.
The driver was written based on the Datasheets for these parts and
generates the audio SSDT information for the amplifiers. Since all
three parts are part of the same family they all have similar SoundWire
settings.
The user can configure which part, SSID and Speaker ID is generated in
ACPI, as well as define each amplifier's Soundwire Unique ID and Link
ID.
These parts support DisCo Version v2.1, but coreboot currently only
supports DisCo v1.0, so ACPI is only generated based on DisCo v1.0.
These parts also support the SDCA v1.0 Specification (from DisCo v2.1)
is also not currently supported by coreboot, therefore SDCA ACPI
properties are also not generated.
This is currently only tested using QEMU using example configuration:
chip drivers/soundwire/cs35l56
# SoundWire Link 2 ID 3
register "desc" = ""Left Speaker Amp""
register "part_id" = "MIPI_DEV_ID_CIRRUS_CS35L56"
register "sub" = ""12345678""
device generic 2.3 on end
end
Which produces the ACPI:
Device (SW23)
{
Name (_ADR, 0x00023301FA355601) // _ADR: Address
Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x0F)
{
Package (0x02)
{
"mipi-sdw-sw-interface-revision",
0x00010000
},
[...]
Package (0x02)
{
"mipi-sdw-source-port-list",
0x18
},
Package (0x02)
{
"mipi-sdw-sink-port-list",
0x06
}
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b") /* Hierarchical Data Extension */,
Package (0x06)
{
Package (0x02)
{
"mipi-sdw-port-bra-mode-0",
"BRA0"
},
Package (0x02)
{
"mipi-sdw-dp-0-subproperties",
"DP0"
},
Package (0x02)
{
"mipi-sdw-dp-1-sink-subproperties",
"SNK1"
},
Package (0x02)
{
"mipi-sdw-dp-2-sink-subproperties",
"SNK2"
},
Package (0x02)
{
"mipi-sdw-dp-3-source-subproperties",
"SRC3"
},
Package (0x02)
{
"mipi-sdw-dp-4-source-subproperties",
"SRC4"
}
}
})
Name (BRA0, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x04)
{
Package (0x02)
{
"mipi-sdw-bra-mode-min-bus-frequency",
Zero
},
Package (0x02)
{
"mipi-sdw-bra-mode-max-bus-frequency",
Zero
},
Package (0x02)
{
"mipi-sdw-bra-mode-max-data-per-frame",
0x01D6
},
Package (0x02)
{
"mipi-sdw-bra-mode-min-us-between-transactions",
Zero
}
}
})
Name (DP0, Package (0x04)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x07)
{
Package (0x02)
{
"mipi-sdw-port-wordlength-configs",
Package (0x03)
{
0x08,
0x10,
0x18
}
},
[...]
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b") /* Hierarchical Data Extension */,
Package (0x01)
{
Package (0x02)
{
"mipi-sdw-port-bra-mode-0",
"BRA0"
}
}
})
Name (SNK1, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x0C)
{
Package (0x02)
{
"mipi-sdw-data-port-type",
Zero
},
Package (0x02)
{
"mipi-sdw-max-grouping-supported",
Zero
},
Package (0x02)
{
"mipi-sdw-imp-def-dpn-interrupts-supported",
Zero
},
Package (0x02)
{
"mipi-sdw-modes-supported",
One
},
Package (0x02)
{
"mipi-sdw-max-async-buffer",
Zero
},
Package (0x02)
{
"mipi-sdw-block-packing-mode",
One
},
Package (0x02)
{
"mipi-sdw-port-encoding-type",
One
},
Package (0x02)
{
"mipi-sdw-port-wordlength-configs",
Package (0x03)
{
0x08,
0x10,
0x18
}
},
Package (0x02)
{
"mipi-sdw-simplified-channelprepare-sm",
Zero
},
Package (0x02)
{
"mipi-sdw-port-channelprepare-timeout",
Zero
},
Package (0x02)
{
"mipi-sdw-channel-number-list",
Package (0x02)
{
Zero,
One
}
},
Package (0x02)
{
"mipi-sdw-channel-combination-list",
Package (0x01)
{
0x03
}
}
}
})
Name (SNK2, Package (0x02)
{
[... same as SNK1 ...]
})
Name (SRC3, Package (0x02)
{
[... same as SNK1 ...]
})
Name (SRC4, Package (0x02)
{
[... same as SNK1 ...]
})
}
Change-Id: Ie04020f008862051f26e0101828b5944d212e706
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89131
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds support for a new Panther Lake B0 SKU CPUID c06c3.
BUG=b:444497427
TEST=Successfully boot a fatcat device with new Panther Lake B0.
coreboot displays the following log:
CPU: ID c06c3, Pantherlake B0, ucode: 0000010c
Change-Id: Id2c1caf8d6845bb16a94314c4e9a214def06efee
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89150
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add mapping of different SKUs based on CPU ID and TDP values.
Add PowerLimits (PL) values.
Add i_trip value for Fast Vmode.
Note: The i_trip value, the value at which the Voltage Regulator (VR)
or SoC will trigger a protective action such as throttling or
entering Fast Vmode is, due to not being documented, currently set at
70% of the maximum current the VR is designed to support for a rail.
The actual i_trip value to be updated once it is available.
Ref=858124 Power Delivery Guide Rev1p0
830097 Powermap Rev1p1
BUG=b:433211504
TEST= Build Ocelot and verify it compiles without any error.
check CPU log for the following error
[ERROR] Could not find the SKU power map
With the current patch this error line is not seen in the CPU log
anymore.
Change-Id: I8c54efc8eb360ed6f814a336448bb204d5ab0268
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88858
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This change introduces `LB_TAG_BOOT_MODE` to the coreboot tables to
convey platform boot information to the payload. The new `lb_boot_mode`
struct uses `enum boot_mode_t` to specify whether the device is booting
in `normal mode`, `low-battery mode` or `off-mode charging`.
This is crucial for platforms where the Application Processor (AP)
manages the charging solution, as it provides the necessary context for
the payload's charger driver. By passing this data through the coreboot
table, we avoid redundant implementation and ensure consistent battery
and charging information is available across both coreboot and the
payload.
A new weak function, `lb_add_boot_mode`, is also introduced. This
function can be overridden by platforms that require this data to add
the boot mode information to the coreboot table.
TEST=Able to build and boot google/quenbi.
Change-Id: I5aea72c02b4d6c856e2504f4007de584c59ee89f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This is a purely cosmetic change to make things slightly more easier to
read. We also only add the IDs which are actively used in the codebase.
TEST=Timeless build produces identical binaries
Change-Id: I4ec0a570020059c85768bab913dff1ba1977e9f9
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88917
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This patch makes DRAM an explicit region by introducing
DECLARE_OPTIONAL_REGION(dram) and DRAM_END().
Note: many SoC platforms determine DRAM size and layout dynamically
during boot, making a static compile-time value is not feasible always.
Attempting to use REGION_SIZE(dram) in this scenario would result in a
missing symbol `_dram_size` error.
By making dram an optional region, we allow its size and address to be
defined only when available, preventing build failures on platforms
that configure DRAM dynamically.
The old extern u8 _dram[] is removed, as it's now covered by the new
region definition.
This is a preparatory step for future changes that will make use of
the new DRAM_END() macro.
This symbol is necessary for systems that require
the DRAM size to be known and accessible from the linker script or
other parts of the build system.
Additionally, a new macro DRAM_END(addr) is defined in memlayout.h.
This macro provides a consistent way to mark the end of the DRAM
region, similar to how REGION_END and other start/end macros are used
throughout the codebase.
TEST=Able to build and boot google/quenbi.
Change-Id: Ib98ec4b991eed56385c83be6a9ca39ff1380ff1b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
DDR5 uses a Serial Presence Detect (SPD) with hub function
(SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of
EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`).
Ref: DDR5 SDRAM spec, JESD79-5C.01
Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
Co-authored-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52731
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors the BMP rendering logic, moving it from
drivers/intel/fsp2_0 to src/lib. This centralizes the code
responsible for rendering BMP images to the framebuffer.
Key changes:
- Move BMP rendering functions (e.g., calculate_logo_coordinates,
copy_logo_to_framebuffer) and their dependencies to
src/lib/render_bmp.c and src/lib/render_bmp.h.
- Decouple BMP definitions from UEFI headers by introducing new
coreboot-specific structures for BMP images and BLT pixels.
- Consolidate bootsplash-related declarations into bootsplash.h,
including new `fw_splash_vertical_alignment`,
`fw_splash_horizontal_alignment`, and `struct logo_config`.
- Update `soc_load_logo_by_coreboot` to use the new common
`load_and_render_logo_to_framebuffer` function and `struct
logo_config` for rendering.
- Relocate `release_logo` to `src/lib/render_bmp.c` for better
module structure.
- Update `src/lib/Makefile.mk` to include the new render_bmp.c.
This refactoring improves code organization and reusability, making
BMP rendering accessible without tight coupling to Intel-specific
driver code.
BUG=b:427387842
TEST=Verify firmware splash screen on google/fatcat.
Change-Id: I0e20ea7e44b4b3ccdb2d4aa9b6aa10ed3447ccfc
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88361
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce cbfs_preload_wait_for_all() to guarantee that all CBFS preload
contexts complete their tasks before moving forward. This function goes
through each preload context and waits for the corresponding thread to
finish by using thread_join(). If any preload thread runs into an issue,
it records an error message along with the context name.
This addition provides a synchronization point during the boot process
which platform code can leverage, typically when the storage backend
supporting asynchronous file transfer is about to be deactivated.
Change-Id: I3ee27ef2fbfdc19bd75532713966f333ad975861
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88457
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently .bss and .data are within the PT_LOAD area of the
bootblock.elf and thus are placed and initialized at the correct spot
when PSP loads the BIOS Reset Image into DRAM.
On S3 resume PSP verifies that the "BIOS Reset Image" is unmodified
before it hands over control to such. Due to the use of BSS and DATA
within the BIOS Reset Image and the modifications of such at previous
boot the verification always fails.
This change moves '.bss' and '.data' out of the *first* PT_LOAD area
and moves it into a separate data_segment also marked PT_LOAD. Since
the second PT_LOAD is ignored by AMDCOMPRESS it doesn't end in the area
being verified at S3 resume. Since '.data' is now part of a separate
PT_LOAD a new region is inserted called '.datacopy' which is filled
by using objcopy. In turn the assembly code in bootblock will memcpy
'.datacopy' to '.data'.
TEST: Can still boot on amd/birman+ and on up/squared.
Change-Id: Id159ade3029060ce2ca6abcb723d5bdfe8841c3a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit introduces a new MCH device ID to support the Wildcat
Lake SoC. It updates the PCI device ID list and platform reporting
logic to accommodate this new ID.
Key changes:
- Add PCI_DID_INTEL_WCL_ID_3 (0xfd02) to the list of recognized
device IDs.
- Update system agent operations to include the new MCH ID.
- Enhance platform reporting to recognize the new MCH ID.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I464fb147f0d3df214ca64b1321eebab08505d7bc
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88248
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
permanent_smi_handler and acpi_s3_resume_allowed returns boolean,
so use boolean instead of int.
Change-Id: I8f390bf3b472519dc41db7daa57b16458961139e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
It causes some name clashes (and therefore overshadowing) of function
names defined in xeon SOC code in later patches of the patch train.
We don't really have a standard naming scheme for callback functions, so
I just added a _func suffix/postfix to indicate the function is a
callback function and to prevent name clashes.
Change-Id: I21811f75ef6e7642a7e4f69997737cd7b8b1cef9
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
